Struct atsamd11c14a::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer.

Used as an argument to the closures in the write and modify methods of the register.

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register.

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 2 - Run in Standby

pub fn lpmux(&mut self) -> LPMUX_W<'_>

Bit 7 - Low-Power Mux

impl W<u8, Reg<u8, _CTRLB>>

pub fn start0(&mut self) -> START0_W<'_>

Bit 0 - Comparator 0 Start Comparison

pub fn start1(&mut self) -> START1_W<'_>

Bit 1 - Comparator 1 Start Comparison

impl W<u16, Reg<u16, _EVCTRL>>

pub fn compeo0(&mut self) -> COMPEO0_W<'_>

Bit 0 - Comparator 0 Event Output Enable

pub fn compeo1(&mut self) -> COMPEO1_W<'_>

Bit 1 - Comparator 1 Event Output Enable

pub fn wineo0(&mut self) -> WINEO0_W<'_>

Bit 4 - Window 0 Event Output Enable

pub fn compei0(&mut self) -> COMPEI0_W<'_>

Bit 8 - Comparator 0 Event Input

pub fn compei1(&mut self) -> COMPEI1_W<'_>

Bit 9 - Comparator 1 Event Input

impl W<u8, Reg<u8, _INTENCLR>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - Comparator 0 Interrupt Enable

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - Comparator 1 Interrupt Enable

pub fn win0(&mut self) -> WIN0_W<'_>

Bit 4 - Window 0 Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - Comparator 0 Interrupt Enable

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - Comparator 1 Interrupt Enable

pub fn win0(&mut self) -> WIN0_W<'_>

Bit 4 - Window 0 Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - Comparator 0

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - Comparator 1

pub fn win0(&mut self) -> WIN0_W<'_>

Bit 4 - Window 0

impl W<u8, Reg<u8, _WINCTRL>>

pub fn wen0(&mut self) -> WEN0_W<'_>

Bit 0 - Window 0 Mode Enable

pub fn wintsel0(&mut self) -> WINTSEL0_W<'_>

Bits 1:2 - Window 0 Interrupt Selection

impl W<u32, Reg<u32, _COMPCTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Enable

pub fn single(&mut self) -> SINGLE_W<'_>

Bit 1 - Single-Shot Mode

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 2:3 - Speed Selection

pub fn intsel(&mut self) -> INTSEL_W<'_>

Bits 5:6 - Interrupt Selection

pub fn muxneg(&mut self) -> MUXNEG_W<'_>

Bits 8:10 - Negative Input Mux Selection

pub fn muxpos(&mut self) -> MUXPOS_W<'_>

Bits 12:13 - Positive Input Mux Selection

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap Inputs and Invert

pub fn out(&mut self) -> OUT_W<'_>

Bits 16:17 - Output

pub fn hyst(&mut self) -> HYST_W<'_>

Bit 19 - Hysteresis Enable

pub fn flen(&mut self) -> FLEN_W<'_>

Bits 24:26 - Filter Length

impl W<u8, Reg<u8, _SCALER>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:5 - Scaler Value

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 2 - Run in Standby

impl W<u8, Reg<u8, _REFCTRL>>

pub fn refsel(&mut self) -> REFSEL_W<'_>

Bits 0:3 - Reference Selection

pub fn refcomp(&mut self) -> REFCOMP_W<'_>

Bit 7 - Reference Buffer Offset Compensation Enable

impl W<u8, Reg<u8, _AVGCTRL>>

pub fn samplenum(&mut self) -> SAMPLENUM_W<'_>

Bits 0:3 - Number of Samples to be Collected

pub fn adjres(&mut self) -> ADJRES_W<'_>

Bits 4:6 - Adjusting Result / Division Coefficient

impl W<u8, Reg<u8, _SAMPCTRL>>

pub fn samplen(&mut self) -> SAMPLEN_W<'_>

Bits 0:5 - Sampling Time Length

impl W<u16, Reg<u16, _CTRLB>>

pub fn diffmode(&mut self) -> DIFFMODE_W<'_>

Bit 0 - Differential Mode

pub fn leftadj(&mut self) -> LEFTADJ_W<'_>

Bit 1 - Left-Adjusted Result

pub fn freerun(&mut self) -> FREERUN_W<'_>

Bit 2 - Free Running Mode

pub fn corren(&mut self) -> CORREN_W<'_>

Bit 3 - Digital Correction Logic Enabled

pub fn ressel(&mut self) -> RESSEL_W<'_>

Bits 4:5 - Conversion Result Resolution

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:10 - Prescaler Configuration

impl W<u8, Reg<u8, _WINCTRL>>

pub fn winmode(&mut self) -> WINMODE_W<'_>

Bits 0:2 - Window Monitor Mode

impl W<u8, Reg<u8, _SWTRIG>>

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 0 - ADC Conversion Flush

pub fn start(&mut self) -> START_W<'_>

Bit 1 - ADC Start Conversion

impl W<u32, Reg<u32, _INPUTCTRL>>

pub fn muxpos(&mut self) -> MUXPOS_W<'_>

Bits 0:4 - Positive Mux Input Selection

pub fn muxneg(&mut self) -> MUXNEG_W<'_>

Bits 8:12 - Negative Mux Input Selection

pub fn inputscan(&mut self) -> INPUTSCAN_W<'_>

Bits 16:19 - Number of Input Channels Included in Scan

pub fn inputoffset(&mut self) -> INPUTOFFSET_W<'_>

Bits 20:23 - Positive Mux Setting Offset

pub fn gain(&mut self) -> GAIN_W<'_>

Bits 24:27 - Gain Factor Selection

impl W<u8, Reg<u8, _EVCTRL>>

pub fn startei(&mut self) -> STARTEI_W<'_>

Bit 0 - Start Conversion Event In

pub fn syncei(&mut self) -> SYNCEI_W<'_>

Bit 1 - Synchronization Event In

pub fn resrdyeo(&mut self) -> RESRDYEO_W<'_>

Bit 4 - Result Ready Event Out

pub fn winmoneo(&mut self) -> WINMONEO_W<'_>

Bit 5 - Window Monitor Event Out

impl W<u8, Reg<u8, _INTENCLR>>

pub fn resrdy(&mut self) -> RESRDY_W<'_>

Bit 0 - Result Ready Interrupt Enable

pub fn overrun(&mut self) -> OVERRUN_W<'_>

Bit 1 - Overrun Interrupt Enable

pub fn winmon(&mut self) -> WINMON_W<'_>

Bit 2 - Window Monitor Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 3 - Synchronization Ready Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn resrdy(&mut self) -> RESRDY_W<'_>

Bit 0 - Result Ready Interrupt Enable

pub fn overrun(&mut self) -> OVERRUN_W<'_>

Bit 1 - Overrun Interrupt Enable

pub fn winmon(&mut self) -> WINMON_W<'_>

Bit 2 - Window Monitor Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 3 - Synchronization Ready Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn resrdy(&mut self) -> RESRDY_W<'_>

Bit 0 - Result Ready

pub fn overrun(&mut self) -> OVERRUN_W<'_>

Bit 1 - Overrun

pub fn winmon(&mut self) -> WINMON_W<'_>

Bit 2 - Window Monitor

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 3 - Synchronization Ready

impl W<u16, Reg<u16, _WINLT>>

pub fn winlt(&mut self) -> WINLT_W<'_>

Bits 0:15 - Window Lower Threshold

impl W<u16, Reg<u16, _WINUT>>

pub fn winut(&mut self) -> WINUT_W<'_>

Bits 0:15 - Window Upper Threshold

impl W<u16, Reg<u16, _GAINCORR>>

pub fn gaincorr(&mut self) -> GAINCORR_W<'_>

Bits 0:11 - Gain Correction Value

impl W<u16, Reg<u16, _OFFSETCORR>>

pub fn offsetcorr(&mut self) -> OFFSETCORR_W<'_>

Bits 0:11 - Offset Correction Value

impl W<u16, Reg<u16, _CALIB>>

pub fn linearity_cal(&mut self) -> LINEARITY_CAL_W<'_>

Bits 0:7 - Linearity Calibration Value

pub fn bias_cal(&mut self) -> BIAS_CAL_W<'_>

Bits 8:10 - Bias Calibration Value

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Run

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 2 - Run in Standby

impl W<u8, Reg<u8, _CTRLB>>

pub fn eoen(&mut self) -> EOEN_W<'_>

Bit 0 - External Output Enable

pub fn ioen(&mut self) -> IOEN_W<'_>

Bit 1 - Internal Output Enable

pub fn leftadj(&mut self) -> LEFTADJ_W<'_>

Bit 2 - Left Adjusted Data

pub fn vpd(&mut self) -> VPD_W<'_>

Bit 3 - Voltage Pump Disable

pub fn bdwp(&mut self) -> BDWP_W<'_>

Bit 4 - Bypass DATABUF Write Protection

pub fn refsel(&mut self) -> REFSEL_W<'_>

Bits 6:7 - Reference Selection

impl W<u8, Reg<u8, _EVCTRL>>

pub fn startei(&mut self) -> STARTEI_W<'_>

Bit 0 - Start Conversion Event Input

pub fn emptyeo(&mut self) -> EMPTYEO_W<'_>

Bit 1 - Data Buffer Empty Event Output

impl W<u8, Reg<u8, _INTENCLR>>

pub fn underrun(&mut self) -> UNDERRUN_W<'_>

Bit 0 - Underrun Interrupt Enable

pub fn empty(&mut self) -> EMPTY_W<'_>

Bit 1 - Data Buffer Empty Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 2 - Synchronization Ready Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn underrun(&mut self) -> UNDERRUN_W<'_>

Bit 0 - Underrun Interrupt Enable

pub fn empty(&mut self) -> EMPTY_W<'_>

Bit 1 - Data Buffer Empty Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 2 - Synchronization Ready Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn underrun(&mut self) -> UNDERRUN_W<'_>

Bit 0 - Underrun

pub fn empty(&mut self) -> EMPTY_W<'_>

Bit 1 - Data Buffer Empty

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 2 - Synchronization Ready

impl W<u16, Reg<u16, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Data value to be converted

impl W<u16, Reg<u16, _DATABUF>>

pub fn databuf(&mut self) -> DATABUF_W<'_>

Bits 0:15 - Data Buffer

impl W<u16, Reg<u16, _CTRL>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn dmaenable(&mut self) -> DMAENABLE_W<'_>

Bit 1 - DMA Enable

pub fn crcenable(&mut self) -> CRCENABLE_W<'_>

Bit 2 - CRC Enable

pub fn lvlen0(&mut self) -> LVLEN0_W<'_>

Bit 8 - Priority Level 0 Enable

pub fn lvlen1(&mut self) -> LVLEN1_W<'_>

Bit 9 - Priority Level 1 Enable

pub fn lvlen2(&mut self) -> LVLEN2_W<'_>

Bit 10 - Priority Level 2 Enable

pub fn lvlen3(&mut self) -> LVLEN3_W<'_>

Bit 11 - Priority Level 3 Enable

impl W<u16, Reg<u16, _CRCCTRL>>

pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W<'_>

Bits 0:1 - CRC Beat Size

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 2:3 - CRC Polynomial Type

pub fn crcsrc(&mut self) -> CRCSRC_W<'_>

Bits 8:13 - CRC Input Source

impl W<u32, Reg<u32, _CRCDATAIN>>

pub fn crcdatain(&mut self) -> CRCDATAIN_W<'_>

Bits 0:31 - CRC Data Input

impl W<u32, Reg<u32, _CRCCHKSUM>>

pub fn crcchksum(&mut self) -> CRCCHKSUM_W<'_>

Bits 0:31 - CRC Checksum

impl W<u8, Reg<u8, _CRCSTATUS>>

pub fn crcbusy(&mut self) -> CRCBUSY_W<'_>

Bit 0 - CRC Module Busy

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Run

impl W<u8, Reg<u8, _QOSCTRL>>

pub fn wrbqos(&mut self) -> WRBQOS_W<'_>

Bits 0:1 - Write-Back Quality of Service

pub fn fqos(&mut self) -> FQOS_W<'_>

Bits 2:3 - Fetch Quality of Service

pub fn dqos(&mut self) -> DQOS_W<'_>

Bits 4:5 - Data Transfer Quality of Service

impl W<u32, Reg<u32, _SWTRIGCTRL>>

pub fn swtrig0(&mut self) -> SWTRIG0_W<'_>

Bit 0 - Channel 0 Software Trigger

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 1 - Channel 1 Software Trigger

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 2 - Channel 2 Software Trigger

pub fn swtrig3(&mut self) -> SWTRIG3_W<'_>

Bit 3 - Channel 3 Software Trigger

pub fn swtrig4(&mut self) -> SWTRIG4_W<'_>

Bit 4 - Channel 4 Software Trigger

pub fn swtrig5(&mut self) -> SWTRIG5_W<'_>

Bit 5 - Channel 5 Software Trigger

impl W<u32, Reg<u32, _PRICTRL0>>

pub fn lvlpri0(&mut self) -> LVLPRI0_W<'_>

Bits 0:2 - Level 0 Channel Priority Number

pub fn rrlvlen0(&mut self) -> RRLVLEN0_W<'_>

Bit 7 - Level 0 Round-Robin Scheduling Enable

pub fn lvlpri1(&mut self) -> LVLPRI1_W<'_>

Bits 8:10 - Level 1 Channel Priority Number

pub fn rrlvlen1(&mut self) -> RRLVLEN1_W<'_>

Bit 15 - Level 1 Round-Robin Scheduling Enable

pub fn lvlpri2(&mut self) -> LVLPRI2_W<'_>

Bits 16:18 - Level 2 Channel Priority Number

pub fn rrlvlen2(&mut self) -> RRLVLEN2_W<'_>

Bit 23 - Level 2 Round-Robin Scheduling Enable

pub fn lvlpri3(&mut self) -> LVLPRI3_W<'_>

Bits 24:26 - Level 3 Channel Priority Number

pub fn rrlvlen3(&mut self) -> RRLVLEN3_W<'_>

Bit 31 - Level 3 Round-Robin Scheduling Enable

impl W<u16, Reg<u16, _INTPEND>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:2 - Channel ID

pub fn terr(&mut self) -> TERR_W<'_>

Bit 8 - Transfer Error

pub fn tcmpl(&mut self) -> TCMPL_W<'_>

Bit 9 - Transfer Complete

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 10 - Channel Suspend

impl W<u32, Reg<u32, _BASEADDR>>

pub fn baseaddr(&mut self) -> BASEADDR_W<'_>

Bits 0:31 - Descriptor Memory Base Address

impl W<u32, Reg<u32, _WRBADDR>>

pub fn wrbaddr(&mut self) -> WRBADDR_W<'_>

Bits 0:31 - Write-Back Memory Base Address

impl W<u8, Reg<u8, _CHID>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:2 - Channel ID

impl W<u8, Reg<u8, _CHCTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Channel Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Channel Enable

impl W<u32, Reg<u32, _CHCTRLB>>

pub fn evact(&mut self) -> EVACT_W<'_>

Bits 0:2 - Event Input Action

pub fn evie(&mut self) -> EVIE_W<'_>

Bit 3 - Channel Event Input Enable

pub fn evoe(&mut self) -> EVOE_W<'_>

Bit 4 - Channel Event Output Enable

pub fn lvl(&mut self) -> LVL_W<'_>

Bits 5:6 - Channel Arbitration Level

pub fn trigsrc(&mut self) -> TRIGSRC_W<'_>

Bits 8:12 - Trigger Source

pub fn trigact(&mut self) -> TRIGACT_W<'_>

Bits 22:23 - Trigger Action

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 24:25 - Software Command

impl W<u8, Reg<u8, _CHINTENCLR>>

pub fn terr(&mut self) -> TERR_W<'_>

Bit 0 - Channel Transfer Error Interrupt Enable

pub fn tcmpl(&mut self) -> TCMPL_W<'_>

Bit 1 - Channel Transfer Complete Interrupt Enable

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 2 - Channel Suspend Interrupt Enable

impl W<u8, Reg<u8, _CHINTENSET>>

pub fn terr(&mut self) -> TERR_W<'_>

Bit 0 - Channel Transfer Error Interrupt Enable

pub fn tcmpl(&mut self) -> TCMPL_W<'_>

Bit 1 - Channel Transfer Complete Interrupt Enable

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 2 - Channel Suspend Interrupt Enable

impl W<u8, Reg<u8, _CHINTFLAG>>

pub fn terr(&mut self) -> TERR_W<'_>

Bit 0 - Channel Transfer Error

pub fn tcmpl(&mut self) -> TCMPL_W<'_>

Bit 1 - Channel Transfer Complete

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 2 - Channel Suspend

impl W<u8, Reg<u8, _CTRL>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn crc(&mut self) -> CRC_W<'_>

Bit 2 - 32-bit Cyclic Redundancy Code

pub fn mbist(&mut self) -> MBIST_W<'_>

Bit 3 - Memory built-in self-test

pub fn ce(&mut self) -> CE_W<'_>

Bit 4 - Chip-Erase

pub fn arr(&mut self) -> ARR_W<'_>

Bit 6 - Auxiliary Row Read

pub fn smsa(&mut self) -> SMSA_W<'_>

Bit 7 - Start Memory Stream Access

impl W<u8, Reg<u8, _STATUSA>>

pub fn done(&mut self) -> DONE_W<'_>

Bit 0 - Done

pub fn crstext(&mut self) -> CRSTEXT_W<'_>

Bit 1 - CPU Reset Phase Extension

pub fn berr(&mut self) -> BERR_W<'_>

Bit 2 - Bus Error

pub fn fail(&mut self) -> FAIL_W<'_>

Bit 3 - Failure

pub fn perr(&mut self) -> PERR_W<'_>

Bit 4 - Protection Error

impl W<u32, Reg<u32, _ADDR>>

pub fn amod(&mut self) -> AMOD_W<'_>

Bits 0:1 - Access Mode

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 2:31 - Address

impl W<u32, Reg<u32, _LENGTH>>

pub fn length(&mut self) -> LENGTH_W<'_>

Bits 2:31 - Length

impl W<u32, Reg<u32, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _DCC>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _DCFG>>

pub fn dcfg(&mut self) -> DCFG_W<'_>

Bits 0:31 - Device Configuration

impl W<u8, Reg<u8, _CTRL>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

impl W<u8, Reg<u8, _NMICTRL>>

pub fn nmisense(&mut self) -> NMISENSE_W<'_>

Bits 0:2 - Non-Maskable Interrupt Sense

pub fn nmifilten(&mut self) -> NMIFILTEN_W<'_>

Bit 3 - Non-Maskable Interrupt Filter Enable

impl W<u8, Reg<u8, _NMIFLAG>>

pub fn nmi(&mut self) -> NMI_W<'_>

Bit 0 - Non-Maskable Interrupt

impl W<u32, Reg<u32, _EVCTRL>>

pub fn extinteo0(&mut self) -> EXTINTEO0_W<'_>

Bit 0 - External Interrupt 0 Event Output Enable

pub fn extinteo1(&mut self) -> EXTINTEO1_W<'_>

Bit 1 - External Interrupt 1 Event Output Enable

pub fn extinteo2(&mut self) -> EXTINTEO2_W<'_>

Bit 2 - External Interrupt 2 Event Output Enable

pub fn extinteo3(&mut self) -> EXTINTEO3_W<'_>

Bit 3 - External Interrupt 3 Event Output Enable

pub fn extinteo4(&mut self) -> EXTINTEO4_W<'_>

Bit 4 - External Interrupt 4 Event Output Enable

pub fn extinteo5(&mut self) -> EXTINTEO5_W<'_>

Bit 5 - External Interrupt 5 Event Output Enable

pub fn extinteo6(&mut self) -> EXTINTEO6_W<'_>

Bit 6 - External Interrupt 6 Event Output Enable

pub fn extinteo7(&mut self) -> EXTINTEO7_W<'_>

Bit 7 - External Interrupt 7 Event Output Enable

impl W<u32, Reg<u32, _INTENCLR>>

pub fn extint0(&mut self) -> EXTINT0_W<'_>

Bit 0 - External Interrupt 0 Enable

pub fn extint1(&mut self) -> EXTINT1_W<'_>

Bit 1 - External Interrupt 1 Enable

pub fn extint2(&mut self) -> EXTINT2_W<'_>

Bit 2 - External Interrupt 2 Enable

pub fn extint3(&mut self) -> EXTINT3_W<'_>

Bit 3 - External Interrupt 3 Enable

pub fn extint4(&mut self) -> EXTINT4_W<'_>

Bit 4 - External Interrupt 4 Enable

pub fn extint5(&mut self) -> EXTINT5_W<'_>

Bit 5 - External Interrupt 5 Enable

pub fn extint6(&mut self) -> EXTINT6_W<'_>

Bit 6 - External Interrupt 6 Enable

pub fn extint7(&mut self) -> EXTINT7_W<'_>

Bit 7 - External Interrupt 7 Enable

impl W<u32, Reg<u32, _INTENSET>>

pub fn extint0(&mut self) -> EXTINT0_W<'_>

Bit 0 - External Interrupt 0 Enable

pub fn extint1(&mut self) -> EXTINT1_W<'_>

Bit 1 - External Interrupt 1 Enable

pub fn extint2(&mut self) -> EXTINT2_W<'_>

Bit 2 - External Interrupt 2 Enable

pub fn extint3(&mut self) -> EXTINT3_W<'_>

Bit 3 - External Interrupt 3 Enable

pub fn extint4(&mut self) -> EXTINT4_W<'_>

Bit 4 - External Interrupt 4 Enable

pub fn extint5(&mut self) -> EXTINT5_W<'_>

Bit 5 - External Interrupt 5 Enable

pub fn extint6(&mut self) -> EXTINT6_W<'_>

Bit 6 - External Interrupt 6 Enable

pub fn extint7(&mut self) -> EXTINT7_W<'_>

Bit 7 - External Interrupt 7 Enable

impl W<u32, Reg<u32, _INTFLAG>>

pub fn extint0(&mut self) -> EXTINT0_W<'_>

Bit 0 - External Interrupt 0

pub fn extint1(&mut self) -> EXTINT1_W<'_>

Bit 1 - External Interrupt 1

pub fn extint2(&mut self) -> EXTINT2_W<'_>

Bit 2 - External Interrupt 2

pub fn extint3(&mut self) -> EXTINT3_W<'_>

Bit 3 - External Interrupt 3

pub fn extint4(&mut self) -> EXTINT4_W<'_>

Bit 4 - External Interrupt 4

pub fn extint5(&mut self) -> EXTINT5_W<'_>

Bit 5 - External Interrupt 5

pub fn extint6(&mut self) -> EXTINT6_W<'_>

Bit 6 - External Interrupt 6

pub fn extint7(&mut self) -> EXTINT7_W<'_>

Bit 7 - External Interrupt 7

impl W<u32, Reg<u32, _WAKEUP>>

pub fn wakeupen0(&mut self) -> WAKEUPEN0_W<'_>

Bit 0 - External Interrupt 0 Wake-up Enable

pub fn wakeupen1(&mut self) -> WAKEUPEN1_W<'_>

Bit 1 - External Interrupt 1 Wake-up Enable

pub fn wakeupen2(&mut self) -> WAKEUPEN2_W<'_>

Bit 2 - External Interrupt 2 Wake-up Enable

pub fn wakeupen3(&mut self) -> WAKEUPEN3_W<'_>

Bit 3 - External Interrupt 3 Wake-up Enable

pub fn wakeupen4(&mut self) -> WAKEUPEN4_W<'_>

Bit 4 - External Interrupt 4 Wake-up Enable

pub fn wakeupen5(&mut self) -> WAKEUPEN5_W<'_>

Bit 5 - External Interrupt 5 Wake-up Enable

pub fn wakeupen6(&mut self) -> WAKEUPEN6_W<'_>

Bit 6 - External Interrupt 6 Wake-up Enable

pub fn wakeupen7(&mut self) -> WAKEUPEN7_W<'_>

Bit 7 - External Interrupt 7 Wake-up Enable

impl W<u32, Reg<u32, _CONFIG>>

pub fn sense0(&mut self) -> SENSE0_W<'_>

Bits 0:2 - Input Sense 0 Configuration

pub fn filten0(&mut self) -> FILTEN0_W<'_>

Bit 3 - Filter 0 Enable

pub fn sense1(&mut self) -> SENSE1_W<'_>

Bits 4:6 - Input Sense 1 Configuration

pub fn filten1(&mut self) -> FILTEN1_W<'_>

Bit 7 - Filter 1 Enable

pub fn sense2(&mut self) -> SENSE2_W<'_>

Bits 8:10 - Input Sense 2 Configuration

pub fn filten2(&mut self) -> FILTEN2_W<'_>

Bit 11 - Filter 2 Enable

pub fn sense3(&mut self) -> SENSE3_W<'_>

Bits 12:14 - Input Sense 3 Configuration

pub fn filten3(&mut self) -> FILTEN3_W<'_>

Bit 15 - Filter 3 Enable

pub fn sense4(&mut self) -> SENSE4_W<'_>

Bits 16:18 - Input Sense 4 Configuration

pub fn filten4(&mut self) -> FILTEN4_W<'_>

Bit 19 - Filter 4 Enable

pub fn sense5(&mut self) -> SENSE5_W<'_>

Bits 20:22 - Input Sense 5 Configuration

pub fn filten5(&mut self) -> FILTEN5_W<'_>

Bit 23 - Filter 5 Enable

pub fn sense6(&mut self) -> SENSE6_W<'_>

Bits 24:26 - Input Sense 6 Configuration

pub fn filten6(&mut self) -> FILTEN6_W<'_>

Bit 27 - Filter 6 Enable

pub fn sense7(&mut self) -> SENSE7_W<'_>

Bits 28:30 - Input Sense 7 Configuration

pub fn filten7(&mut self) -> FILTEN7_W<'_>

Bit 31 - Filter 7 Enable

impl W<u8, Reg<u8, _CTRL>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn gclkreq(&mut self) -> GCLKREQ_W<'_>

Bit 4 - Generic Clock Requests

impl W<u32, Reg<u32, _CHANNEL>>

pub fn channel(&mut self) -> CHANNEL_W<'_>

Bits 0:2 - Channel Selection

pub fn swevt(&mut self) -> SWEVT_W<'_>

Bit 8 - Software Event

pub fn evgen(&mut self) -> EVGEN_W<'_>

Bits 16:21 - Event Generator Selection

pub fn path(&mut self) -> PATH_W<'_>

Bits 24:25 - Path Selection

pub fn edgsel(&mut self) -> EDGSEL_W<'_>

Bits 26:27 - Edge Detection Selection

impl W<u16, Reg<u16, _USER>>

pub fn user(&mut self) -> USER_W<'_>

Bits 0:4 - User Multiplexer Selection

pub fn channel(&mut self) -> CHANNEL_W<'_>

Bits 8:11 - Channel Event Selection

impl W<u32, Reg<u32, _INTENCLR>>

pub fn ovr0(&mut self) -> OVR0_W<'_>

Bit 0 - Channel 0 Overrun Interrupt Enable

pub fn ovr1(&mut self) -> OVR1_W<'_>

Bit 1 - Channel 1 Overrun Interrupt Enable

pub fn ovr2(&mut self) -> OVR2_W<'_>

Bit 2 - Channel 2 Overrun Interrupt Enable

pub fn ovr3(&mut self) -> OVR3_W<'_>

Bit 3 - Channel 3 Overrun Interrupt Enable

pub fn ovr4(&mut self) -> OVR4_W<'_>

Bit 4 - Channel 4 Overrun Interrupt Enable

pub fn ovr5(&mut self) -> OVR5_W<'_>

Bit 5 - Channel 5 Overrun Interrupt Enable

pub fn evd0(&mut self) -> EVD0_W<'_>

Bit 8 - Channel 0 Event Detection Interrupt Enable

pub fn evd1(&mut self) -> EVD1_W<'_>

Bit 9 - Channel 1 Event Detection Interrupt Enable

pub fn evd2(&mut self) -> EVD2_W<'_>

Bit 10 - Channel 2 Event Detection Interrupt Enable

pub fn evd3(&mut self) -> EVD3_W<'_>

Bit 11 - Channel 3 Event Detection Interrupt Enable

pub fn evd4(&mut self) -> EVD4_W<'_>

Bit 12 - Channel 4 Event Detection Interrupt Enable

pub fn evd5(&mut self) -> EVD5_W<'_>

Bit 13 - Channel 5 Event Detection Interrupt Enable

impl W<u32, Reg<u32, _INTENSET>>

pub fn ovr0(&mut self) -> OVR0_W<'_>

Bit 0 - Channel 0 Overrun Interrupt Enable

pub fn ovr1(&mut self) -> OVR1_W<'_>

Bit 1 - Channel 1 Overrun Interrupt Enable

pub fn ovr2(&mut self) -> OVR2_W<'_>

Bit 2 - Channel 2 Overrun Interrupt Enable

pub fn ovr3(&mut self) -> OVR3_W<'_>

Bit 3 - Channel 3 Overrun Interrupt Enable

pub fn ovr4(&mut self) -> OVR4_W<'_>

Bit 4 - Channel 4 Overrun Interrupt Enable

pub fn ovr5(&mut self) -> OVR5_W<'_>

Bit 5 - Channel 5 Overrun Interrupt Enable

pub fn evd0(&mut self) -> EVD0_W<'_>

Bit 8 - Channel 0 Event Detection Interrupt Enable

pub fn evd1(&mut self) -> EVD1_W<'_>

Bit 9 - Channel 1 Event Detection Interrupt Enable

pub fn evd2(&mut self) -> EVD2_W<'_>

Bit 10 - Channel 2 Event Detection Interrupt Enable

pub fn evd3(&mut self) -> EVD3_W<'_>

Bit 11 - Channel 3 Event Detection Interrupt Enable

pub fn evd4(&mut self) -> EVD4_W<'_>

Bit 12 - Channel 4 Event Detection Interrupt Enable

pub fn evd5(&mut self) -> EVD5_W<'_>

Bit 13 - Channel 5 Event Detection Interrupt Enable

impl W<u32, Reg<u32, _INTFLAG>>

pub fn ovr0(&mut self) -> OVR0_W<'_>

Bit 0 - Channel 0 Overrun

pub fn ovr1(&mut self) -> OVR1_W<'_>

Bit 1 - Channel 1 Overrun

pub fn ovr2(&mut self) -> OVR2_W<'_>

Bit 2 - Channel 2 Overrun

pub fn ovr3(&mut self) -> OVR3_W<'_>

Bit 3 - Channel 3 Overrun

pub fn ovr4(&mut self) -> OVR4_W<'_>

Bit 4 - Channel 4 Overrun

pub fn ovr5(&mut self) -> OVR5_W<'_>

Bit 5 - Channel 5 Overrun

pub fn evd0(&mut self) -> EVD0_W<'_>

Bit 8 - Channel 0 Event Detection

pub fn evd1(&mut self) -> EVD1_W<'_>

Bit 9 - Channel 1 Event Detection

pub fn evd2(&mut self) -> EVD2_W<'_>

Bit 10 - Channel 2 Event Detection

pub fn evd3(&mut self) -> EVD3_W<'_>

Bit 11 - Channel 3 Event Detection

pub fn evd4(&mut self) -> EVD4_W<'_>

Bit 12 - Channel 4 Event Detection

pub fn evd5(&mut self) -> EVD5_W<'_>

Bit 13 - Channel 5 Event Detection

impl W<u8, Reg<u8, _CTRL>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

impl W<u16, Reg<u16, _CLKCTRL>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:5 - Generic Clock Selection ID

pub fn gen(&mut self) -> GEN_W<'_>

Bits 8:11 - Generic Clock Generator

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 14 - Clock Enable

pub fn wrtlock(&mut self) -> WRTLOCK_W<'_>

Bit 15 - Write Lock

impl W<u32, Reg<u32, _GENCTRL>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:3 - Generic Clock Generator Selection

pub fn src(&mut self) -> SRC_W<'_>

Bits 8:12 - Source Select

pub fn genen(&mut self) -> GENEN_W<'_>

Bit 16 - Generic Clock Generator Enable

pub fn idc(&mut self) -> IDC_W<'_>

Bit 17 - Improve Duty Cycle

pub fn oov(&mut self) -> OOV_W<'_>

Bit 18 - Output Off Value

pub fn oe(&mut self) -> OE_W<'_>

Bit 19 - Output Enable

pub fn divsel(&mut self) -> DIVSEL_W<'_>

Bit 20 - Divide Selection

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 21 - Run in Standby

impl W<u32, Reg<u32, _GENDIV>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:3 - Generic Clock Generator Selection

pub fn div(&mut self) -> DIV_W<'_>

Bits 8:23 - Division Factor

impl W<u32, Reg<u32, _PRAS>>

pub fn m0pr(&mut self) -> M0PR_W<'_>

Bits 0:3 - Master 0 Priority

pub fn m1pr(&mut self) -> M1PR_W<'_>

Bits 4:7 - Master 1 Priority

pub fn m2pr(&mut self) -> M2PR_W<'_>

Bits 8:11 - Master 2 Priority

pub fn m3pr(&mut self) -> M3PR_W<'_>

Bits 12:15 - Master 3 Priority

pub fn m4pr(&mut self) -> M4PR_W<'_>

Bits 16:19 - Master 4 Priority

pub fn m5pr(&mut self) -> M5PR_W<'_>

Bits 20:23 - Master 5 Priority

pub fn m6pr(&mut self) -> M6PR_W<'_>

Bits 24:27 - Master 6 Priority

pub fn m7pr(&mut self) -> M7PR_W<'_>

Bits 28:31 - Master 7 Priority

impl W<u32, Reg<u32, _PRBS>>

pub fn m8pr(&mut self) -> M8PR_W<'_>

Bits 0:3 - Master 8 Priority

pub fn m9pr(&mut self) -> M9PR_W<'_>

Bits 4:7 - Master 9 Priority

pub fn m10pr(&mut self) -> M10PR_W<'_>

Bits 8:11 - Master 10 Priority

pub fn m11pr(&mut self) -> M11PR_W<'_>

Bits 12:15 - Master 11 Priority

pub fn m12pr(&mut self) -> M12PR_W<'_>

Bits 16:19 - Master 12 Priority

pub fn m13pr(&mut self) -> M13PR_W<'_>

Bits 20:23 - Master 13 Priority

pub fn m14pr(&mut self) -> M14PR_W<'_>

Bits 24:27 - Master 14 Priority

pub fn m15pr(&mut self) -> M15PR_W<'_>

Bits 28:31 - Master 15 Priority

impl W<u32, Reg<u32, _SFR>>

pub fn sfr(&mut self) -> SFR_W<'_>

Bits 0:31 - Special Function Register

impl W<u32, Reg<u32, _POSITION>>

pub fn wrap(&mut self) -> WRAP_W<'_>

Bit 2 - Pointer Value Wraps

pub fn pointer(&mut self) -> POINTER_W<'_>

Bits 3:31 - Trace Packet Location Pointer

impl W<u32, Reg<u32, _MASTER>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 0:4 - Maximum Value of the Trace Buffer in SRAM

pub fn tstarten(&mut self) -> TSTARTEN_W<'_>

Bit 5 - Trace Start Input Enable

pub fn tstopen(&mut self) -> TSTOPEN_W<'_>

Bit 6 - Trace Stop Input Enable

pub fn sfrwpriv(&mut self) -> SFRWPRIV_W<'_>

Bit 7 - Special Function Register Write Privilege

pub fn rampriv(&mut self) -> RAMPRIV_W<'_>

Bit 8 - SRAM Privilege

pub fn haltreq(&mut self) -> HALTREQ_W<'_>

Bit 9 - Halt Request

pub fn en(&mut self) -> EN_W<'_>

Bit 31 - Main Trace Enable

impl W<u32, Reg<u32, _FLOW>>

pub fn autostop(&mut self) -> AUTOSTOP_W<'_>

Bit 0 - Auto Stop Tracing

pub fn autohalt(&mut self) -> AUTOHALT_W<'_>

Bit 1 - Auto Halt Request

pub fn watermark(&mut self) -> WATERMARK_W<'_>

Bits 3:31 - Watermark value

impl W<u16, Reg<u16, _CTRLA>>

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 0:6 - Command

pub fn cmdex(&mut self) -> CMDEX_W<'_>

Bits 8:15 - Command Execution

impl W<u32, Reg<u32, _CTRLB>>

pub fn rws(&mut self) -> RWS_W<'_>

Bits 1:4 - NVM Read Wait States

pub fn manw(&mut self) -> MANW_W<'_>

Bit 7 - Manual Write

pub fn sleepprm(&mut self) -> SLEEPPRM_W<'_>

Bits 8:9 - Power Reduction Mode during Sleep

pub fn readmode(&mut self) -> READMODE_W<'_>

Bits 16:17 - NVMCTRL Read Mode

pub fn cachedis(&mut self) -> CACHEDIS_W<'_>

Bit 18 - Cache Disable

impl W<u8, Reg<u8, _INTENCLR>>

pub fn ready(&mut self) -> READY_W<'_>

Bit 0 - NVM Ready Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 1 - Error Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn ready(&mut self) -> READY_W<'_>

Bit 0 - NVM Ready Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 1 - Error Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn error(&mut self) -> ERROR_W<'_>

Bit 1 - Error

impl W<u16, Reg<u16, _STATUS>>

pub fn load(&mut self) -> LOAD_W<'_>

Bit 1 - NVM Page Buffer Active Loading

pub fn proge(&mut self) -> PROGE_W<'_>

Bit 2 - Programming Error Status

pub fn locke(&mut self) -> LOCKE_W<'_>

Bit 3 - Lock Error Status

pub fn nvme(&mut self) -> NVME_W<'_>

Bit 4 - NVM Error

impl W<u32, Reg<u32, _ADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:21 - NVM Address

impl W<u32, Reg<u32, _WPCLR>>

pub fn wp(&mut self) -> WP_W<'_>

Bits 1:31 - Write Protection Clear

impl W<u32, Reg<u32, _WPSET>>

pub fn wp(&mut self) -> WP_W<'_>

Bits 1:31 - Write Protection Set

impl W<u8, Reg<u8, _CTRL>>

pub fn cfden(&mut self) -> CFDEN_W<'_>

Bit 2 - Clock Failure Detector Enable

pub fn bkupclk(&mut self) -> BKUPCLK_W<'_>

Bit 4 - Backup Clock Select

impl W<u8, Reg<u8, _SLEEP>>

pub fn idle(&mut self) -> IDLE_W<'_>

Bits 0:1 - Idle Mode Configuration

impl W<u8, Reg<u8, _EXTCTRL>>

pub fn setdis(&mut self) -> SETDIS_W<'_>

Bit 0 - External Reset Disable

impl W<u8, Reg<u8, _CPUSEL>>

pub fn cpudiv(&mut self) -> CPUDIV_W<'_>

Bits 0:2 - CPU Prescaler Selection

impl W<u8, Reg<u8, _APBASEL>>

pub fn apbadiv(&mut self) -> APBADIV_W<'_>

Bits 0:2 - APBA Prescaler Selection

impl W<u8, Reg<u8, _APBBSEL>>

pub fn apbbdiv(&mut self) -> APBBDIV_W<'_>

Bits 0:2 - APBB Prescaler Selection

impl W<u8, Reg<u8, _APBCSEL>>

pub fn apbcdiv(&mut self) -> APBCDIV_W<'_>

Bits 0:2 - APBC Prescaler Selection

impl W<u32, Reg<u32, _AHBMASK>>

pub fn hpb0_(&mut self) -> HPB0__W<'_>

Bit 0 - HPB0 AHB Clock Mask

pub fn hpb1_(&mut self) -> HPB1__W<'_>

Bit 1 - HPB1 AHB Clock Mask

pub fn hpb2_(&mut self) -> HPB2__W<'_>

Bit 2 - HPB2 AHB Clock Mask

pub fn dsu_(&mut self) -> DSU__W<'_>

Bit 3 - DSU AHB Clock Mask

pub fn nvmctrl_(&mut self) -> NVMCTRL__W<'_>

Bit 4 - NVMCTRL AHB Clock Mask

pub fn dmac_(&mut self) -> DMAC__W<'_>

Bit 5 - DMAC AHB Clock Mask

pub fn usb_(&mut self) -> USB__W<'_>

Bit 6 - USB AHB Clock Mask

impl W<u32, Reg<u32, _APBAMASK>>

pub fn pac0_(&mut self) -> PAC0__W<'_>

Bit 0 - PAC0 APB Clock Enable

pub fn pm_(&mut self) -> PM__W<'_>

Bit 1 - PM APB Clock Enable

pub fn sysctrl_(&mut self) -> SYSCTRL__W<'_>

Bit 2 - SYSCTRL APB Clock Enable

pub fn gclk_(&mut self) -> GCLK__W<'_>

Bit 3 - GCLK APB Clock Enable

pub fn wdt_(&mut self) -> WDT__W<'_>

Bit 4 - WDT APB Clock Enable

pub fn rtc_(&mut self) -> RTC__W<'_>

Bit 5 - RTC APB Clock Enable

pub fn eic_(&mut self) -> EIC__W<'_>

Bit 6 - EIC APB Clock Enable

impl W<u32, Reg<u32, _APBBMASK>>

pub fn pac1_(&mut self) -> PAC1__W<'_>

Bit 0 - PAC1 APB Clock Enable

pub fn dsu_(&mut self) -> DSU__W<'_>

Bit 1 - DSU APB Clock Enable

pub fn nvmctrl_(&mut self) -> NVMCTRL__W<'_>

Bit 2 - NVMCTRL APB Clock Enable

pub fn port_(&mut self) -> PORT__W<'_>

Bit 3 - PORT APB Clock Enable

pub fn dmac_(&mut self) -> DMAC__W<'_>

Bit 4 - DMAC APB Clock Enable

pub fn usb_(&mut self) -> USB__W<'_>

Bit 5 - USB APB Clock Enable

pub fn hmatrix_(&mut self) -> HMATRIX__W<'_>

Bit 6 - HMATRIX APB Clock Enable

impl W<u32, Reg<u32, _APBCMASK>>

pub fn pac2_(&mut self) -> PAC2__W<'_>

Bit 0 - PAC2 APB Clock Enable

pub fn evsys_(&mut self) -> EVSYS__W<'_>

Bit 1 - EVSYS APB Clock Enable

pub fn sercom0_(&mut self) -> SERCOM0__W<'_>

Bit 2 - SERCOM0 APB Clock Enable

pub fn sercom1_(&mut self) -> SERCOM1__W<'_>

Bit 3 - SERCOM1 APB Clock Enable

pub fn tcc0_(&mut self) -> TCC0__W<'_>

Bit 5 - TCC0 APB Clock Enable

pub fn tc1_(&mut self) -> TC1__W<'_>

Bit 6 - TC1 APB Clock Enable

pub fn tc2_(&mut self) -> TC2__W<'_>

Bit 7 - TC2 APB Clock Enable

pub fn adc_(&mut self) -> ADC__W<'_>

Bit 8 - ADC APB Clock Enable

pub fn ac_(&mut self) -> AC__W<'_>

Bit 9 - AC APB Clock Enable

pub fn dac_(&mut self) -> DAC__W<'_>

Bit 10 - DAC APB Clock Enable

pub fn ptc_(&mut self) -> PTC__W<'_>

Bit 11 - PTC APB Clock Enable

impl W<u8, Reg<u8, _INTENCLR>>

pub fn ckrdy(&mut self) -> CKRDY_W<'_>

Bit 0 - Clock Ready Interrupt Enable

pub fn cfd(&mut self) -> CFD_W<'_>

Bit 1 - Clock Failure Detector Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn ckrdy(&mut self) -> CKRDY_W<'_>

Bit 0 - Clock Ready Interrupt Enable

pub fn cfd(&mut self) -> CFD_W<'_>

Bit 1 - Clock Failure Detector Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn ckrdy(&mut self) -> CKRDY_W<'_>

Bit 0 - Clock Ready

pub fn cfd(&mut self) -> CFD_W<'_>

Bit 1 - Clock Failure Detector

impl W<u32, Reg<u32, _DIR>>

pub fn dir(&mut self) -> DIR_W<'_>

Bits 0:31 - Port Data Direction

impl W<u32, Reg<u32, _DIRCLR>>

pub fn dirclr(&mut self) -> DIRCLR_W<'_>

Bits 0:31 - Port Data Direction Clear

impl W<u32, Reg<u32, _DIRSET>>

pub fn dirset(&mut self) -> DIRSET_W<'_>

Bits 0:31 - Port Data Direction Set

impl W<u32, Reg<u32, _DIRTGL>>

pub fn dirtgl(&mut self) -> DIRTGL_W<'_>

Bits 0:31 - Port Data Direction Toggle

impl W<u32, Reg<u32, _OUT>>

pub fn out(&mut self) -> OUT_W<'_>

Bits 0:31 - Port Data Output Value

impl W<u32, Reg<u32, _OUTCLR>>

pub fn outclr(&mut self) -> OUTCLR_W<'_>

Bits 0:31 - Port Data Output Value Clear

impl W<u32, Reg<u32, _OUTSET>>

pub fn outset(&mut self) -> OUTSET_W<'_>

Bits 0:31 - Port Data Output Value Set

impl W<u32, Reg<u32, _OUTTGL>>

pub fn outtgl(&mut self) -> OUTTGL_W<'_>

Bits 0:31 - Port Data Output Value Toggle

impl W<u32, Reg<u32, _CTRL>>

pub fn sampling(&mut self) -> SAMPLING_W<'_>

Bits 0:31 - Input Sampling Mode

impl W<u32, Reg<u32, _WRCONFIG>>

pub fn pinmask(&mut self) -> PINMASK_W<'_>

Bits 0:15 - Pin Mask for Multiple Pin Configuration

pub fn pmuxen(&mut self) -> PMUXEN_W<'_>

Bit 16 - Peripheral Multiplexer Enable

pub fn inen(&mut self) -> INEN_W<'_>

Bit 17 - Input Enable

pub fn pullen(&mut self) -> PULLEN_W<'_>

Bit 18 - Pull Enable

pub fn drvstr(&mut self) -> DRVSTR_W<'_>

Bit 22 - Output Driver Strength Selection

pub fn pmux(&mut self) -> PMUX_W<'_>

Bits 24:27 - Peripheral Multiplexing

pub fn wrpmux(&mut self) -> WRPMUX_W<'_>

Bit 28 - Write PMUX

pub fn wrpincfg(&mut self) -> WRPINCFG_W<'_>

Bit 30 - Write PINCFG

pub fn hwsel(&mut self) -> HWSEL_W<'_>

Bit 31 - Half-Word Select

impl W<u8, Reg<u8, _PMUX0_>>

pub fn pmuxe(&mut self) -> PMUXE_W<'_>

Bits 0:3 - Peripheral Multiplexing Even

pub fn pmuxo(&mut self) -> PMUXO_W<'_>

Bits 4:7 - Peripheral Multiplexing Odd

impl W<u8, Reg<u8, _PINCFG0_>>

pub fn pmuxen(&mut self) -> PMUXEN_W<'_>

Bit 0 - Peripheral Multiplexer Enable

pub fn inen(&mut self) -> INEN_W<'_>

Bit 1 - Input Enable

pub fn pullen(&mut self) -> PULLEN_W<'_>

Bit 2 - Pull Enable

pub fn drvstr(&mut self) -> DRVSTR_W<'_>

Bit 6 - Output Driver Strength Selection

impl W<u16, Reg<u16, _CTRL>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - Operating Mode

pub fn matchclr(&mut self) -> MATCHCLR_W<'_>

Bit 7 - Clear on Match

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:11 - Prescaler

impl W<u16, Reg<u16, _READREQ>>

pub fn rcont(&mut self) -> RCONT_W<'_>

Bit 14 - Read Continuously

pub fn rreq(&mut self) -> RREQ_W<'_>

Bit 15 - Read Request

impl W<u16, Reg<u16, _EVCTRL>>

pub fn pereo0(&mut self) -> PEREO0_W<'_>

Bit 0 - Periodic Interval 0 Event Output Enable

pub fn pereo1(&mut self) -> PEREO1_W<'_>

Bit 1 - Periodic Interval 1 Event Output Enable

pub fn pereo2(&mut self) -> PEREO2_W<'_>

Bit 2 - Periodic Interval 2 Event Output Enable

pub fn pereo3(&mut self) -> PEREO3_W<'_>

Bit 3 - Periodic Interval 3 Event Output Enable

pub fn pereo4(&mut self) -> PEREO4_W<'_>

Bit 4 - Periodic Interval 4 Event Output Enable

pub fn pereo5(&mut self) -> PEREO5_W<'_>

Bit 5 - Periodic Interval 5 Event Output Enable

pub fn pereo6(&mut self) -> PEREO6_W<'_>

Bit 6 - Periodic Interval 6 Event Output Enable

pub fn pereo7(&mut self) -> PEREO7_W<'_>

Bit 7 - Periodic Interval 7 Event Output Enable

pub fn cmpeo0(&mut self) -> CMPEO0_W<'_>

Bit 8 - Compare 0 Event Output Enable

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 15 - Overflow Event Output Enable

impl W<u8, Reg<u8, _INTENCLR>>

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 0 - Compare 0 Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 6 - Synchronization Ready Interrupt Enable

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 7 - Overflow Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 0 - Compare 0 Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 6 - Synchronization Ready Interrupt Enable

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 7 - Overflow Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 0 - Compare 0

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 6 - Synchronization Ready

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 7 - Overflow

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Run During Debug

impl W<u8, Reg<u8, _FREQCORR>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:6 - Correction Value

pub fn sign(&mut self) -> SIGN_W<'_>

Bit 7 - Correction Sign

impl W<u32, Reg<u32, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _COMP>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:31 - Compare Value

impl W<u16, Reg<u16, _CTRL>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - Operating Mode

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:11 - Prescaler

impl W<u16, Reg<u16, _READREQ>>

pub fn rcont(&mut self) -> RCONT_W<'_>

Bit 14 - Read Continuously

pub fn rreq(&mut self) -> RREQ_W<'_>

Bit 15 - Read Request

impl W<u16, Reg<u16, _EVCTRL>>

pub fn pereo0(&mut self) -> PEREO0_W<'_>

Bit 0 - Periodic Interval 0 Event Output Enable

pub fn pereo1(&mut self) -> PEREO1_W<'_>

Bit 1 - Periodic Interval 1 Event Output Enable

pub fn pereo2(&mut self) -> PEREO2_W<'_>

Bit 2 - Periodic Interval 2 Event Output Enable

pub fn pereo3(&mut self) -> PEREO3_W<'_>

Bit 3 - Periodic Interval 3 Event Output Enable

pub fn pereo4(&mut self) -> PEREO4_W<'_>

Bit 4 - Periodic Interval 4 Event Output Enable

pub fn pereo5(&mut self) -> PEREO5_W<'_>

Bit 5 - Periodic Interval 5 Event Output Enable

pub fn pereo6(&mut self) -> PEREO6_W<'_>

Bit 6 - Periodic Interval 6 Event Output Enable

pub fn pereo7(&mut self) -> PEREO7_W<'_>

Bit 7 - Periodic Interval 7 Event Output Enable

pub fn cmpeo0(&mut self) -> CMPEO0_W<'_>

Bit 8 - Compare 0 Event Output Enable

pub fn cmpeo1(&mut self) -> CMPEO1_W<'_>

Bit 9 - Compare 1 Event Output Enable

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 15 - Overflow Event Output Enable

impl W<u8, Reg<u8, _INTENCLR>>

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 0 - Compare 0 Interrupt Enable

pub fn cmp1(&mut self) -> CMP1_W<'_>

Bit 1 - Compare 1 Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 6 - Synchronization Ready Interrupt Enable

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 7 - Overflow Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 0 - Compare 0 Interrupt Enable

pub fn cmp1(&mut self) -> CMP1_W<'_>

Bit 1 - Compare 1 Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 6 - Synchronization Ready Interrupt Enable

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 7 - Overflow Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 0 - Compare 0

pub fn cmp1(&mut self) -> CMP1_W<'_>

Bit 1 - Compare 1

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 6 - Synchronization Ready

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 7 - Overflow

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Run During Debug

impl W<u8, Reg<u8, _FREQCORR>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:6 - Correction Value

pub fn sign(&mut self) -> SIGN_W<'_>

Bit 7 - Correction Sign

impl W<u16, Reg<u16, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Counter Value

impl W<u16, Reg<u16, _PER>>

pub fn per(&mut self) -> PER_W<'_>

Bits 0:15 - Counter Period

impl W<u16, Reg<u16, _COMP>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:15 - Compare Value

impl W<u16, Reg<u16, _CTRL>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - Operating Mode

pub fn clkrep(&mut self) -> CLKREP_W<'_>

Bit 6 - Clock Representation

pub fn matchclr(&mut self) -> MATCHCLR_W<'_>

Bit 7 - Clear on Match

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:11 - Prescaler

impl W<u16, Reg<u16, _READREQ>>

pub fn rcont(&mut self) -> RCONT_W<'_>

Bit 14 - Read Continuously

pub fn rreq(&mut self) -> RREQ_W<'_>

Bit 15 - Read Request

impl W<u16, Reg<u16, _EVCTRL>>

pub fn pereo0(&mut self) -> PEREO0_W<'_>

Bit 0 - Periodic Interval 0 Event Output Enable

pub fn pereo1(&mut self) -> PEREO1_W<'_>

Bit 1 - Periodic Interval 1 Event Output Enable

pub fn pereo2(&mut self) -> PEREO2_W<'_>

Bit 2 - Periodic Interval 2 Event Output Enable

pub fn pereo3(&mut self) -> PEREO3_W<'_>

Bit 3 - Periodic Interval 3 Event Output Enable

pub fn pereo4(&mut self) -> PEREO4_W<'_>

Bit 4 - Periodic Interval 4 Event Output Enable

pub fn pereo5(&mut self) -> PEREO5_W<'_>

Bit 5 - Periodic Interval 5 Event Output Enable

pub fn pereo6(&mut self) -> PEREO6_W<'_>

Bit 6 - Periodic Interval 6 Event Output Enable

pub fn pereo7(&mut self) -> PEREO7_W<'_>

Bit 7 - Periodic Interval 7 Event Output Enable

pub fn alarmeo0(&mut self) -> ALARMEO0_W<'_>

Bit 8 - Alarm 0 Event Output Enable

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 15 - Overflow Event Output Enable

impl W<u8, Reg<u8, _INTENCLR>>

pub fn alarm0(&mut self) -> ALARM0_W<'_>

Bit 0 - Alarm 0 Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 6 - Synchronization Ready Interrupt Enable

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 7 - Overflow Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn alarm0(&mut self) -> ALARM0_W<'_>

Bit 0 - Alarm 0 Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 6 - Synchronization Ready Interrupt Enable

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 7 - Overflow Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn alarm0(&mut self) -> ALARM0_W<'_>

Bit 0 - Alarm 0

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 6 - Synchronization Ready

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 7 - Overflow

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Run During Debug

impl W<u8, Reg<u8, _FREQCORR>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:6 - Correction Value

pub fn sign(&mut self) -> SIGN_W<'_>

Bit 7 - Correction Sign

impl W<u32, Reg<u32, _CLOCK>>

pub fn second(&mut self) -> SECOND_W<'_>

Bits 0:5 - Second

pub fn minute(&mut self) -> MINUTE_W<'_>

Bits 6:11 - Minute

pub fn hour(&mut self) -> HOUR_W<'_>

Bits 12:16 - Hour

pub fn day(&mut self) -> DAY_W<'_>

Bits 17:21 - Day

pub fn month(&mut self) -> MONTH_W<'_>

Bits 22:25 - Month

pub fn year(&mut self) -> YEAR_W<'_>

Bits 26:31 - Year

impl W<u32, Reg<u32, _ALARM>>

pub fn second(&mut self) -> SECOND_W<'_>

Bits 0:5 - Second

pub fn minute(&mut self) -> MINUTE_W<'_>

Bits 6:11 - Minute

pub fn hour(&mut self) -> HOUR_W<'_>

Bits 12:16 - Hour

pub fn day(&mut self) -> DAY_W<'_>

Bits 17:21 - Day

pub fn month(&mut self) -> MONTH_W<'_>

Bits 22:25 - Month

pub fn year(&mut self) -> YEAR_W<'_>

Bits 26:31 - Year

impl W<u8, Reg<u8, _MASK>>

pub fn sel(&mut self) -> SEL_W<'_>

Bits 0:2 - Alarm Mask Selection

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:4 - Operating Mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 7 - Run in Standby

pub fn pinout(&mut self) -> PINOUT_W<'_>

Bit 16 - Pin Usage

pub fn sdahold(&mut self) -> SDAHOLD_W<'_>

Bits 20:21 - SDA Hold Time

pub fn mexttoen(&mut self) -> MEXTTOEN_W<'_>

Bit 22 - Master SCL Low Extend Timeout

pub fn sexttoen(&mut self) -> SEXTTOEN_W<'_>

Bit 23 - Slave SCL Low Extend Timeout

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 24:25 - Transfer Speed

pub fn sclsm(&mut self) -> SCLSM_W<'_>

Bit 27 - SCL Clock Stretch Mode

pub fn inactout(&mut self) -> INACTOUT_W<'_>

Bits 28:29 - Inactive Time-Out

pub fn lowtouten(&mut self) -> LOWTOUTEN_W<'_>

Bit 30 - SCL Low Timeout Enable

impl W<u32, Reg<u32, _CTRLB>>

pub fn smen(&mut self) -> SMEN_W<'_>

Bit 8 - Smart Mode Enable

pub fn qcen(&mut self) -> QCEN_W<'_>

Bit 9 - Quick Command Enable

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 16:17 - Command

pub fn ackact(&mut self) -> ACKACT_W<'_>

Bit 18 - Acknowledge Action

impl W<u32, Reg<u32, _BAUD>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:7 - Baud Rate Value

pub fn baudlow(&mut self) -> BAUDLOW_W<'_>

Bits 8:15 - Baud Rate Value Low

pub fn hsbaud(&mut self) -> HSBAUD_W<'_>

Bits 16:23 - High Speed Baud Rate Value

pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W<'_>

Bits 24:31 - High Speed Baud Rate Value Low

impl W<u8, Reg<u8, _INTENCLR>>

pub fn mb(&mut self) -> MB_W<'_>

Bit 0 - Master On Bus Interrupt Disable

pub fn sb(&mut self) -> SB_W<'_>

Bit 1 - Slave On Bus Interrupt Disable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn mb(&mut self) -> MB_W<'_>

Bit 0 - Master On Bus Interrupt Enable

pub fn sb(&mut self) -> SB_W<'_>

Bit 1 - Slave On Bus Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn mb(&mut self) -> MB_W<'_>

Bit 0 - Master On Bus Interrupt

pub fn sb(&mut self) -> SB_W<'_>

Bit 1 - Slave On Bus Interrupt

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt

impl W<u16, Reg<u16, _STATUS>>

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 0 - Bus Error

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 1 - Arbitration Lost

pub fn busstate(&mut self) -> BUSSTATE_W<'_>

Bits 4:5 - Bus State

pub fn lowtout(&mut self) -> LOWTOUT_W<'_>

Bit 6 - SCL Low Timeout

pub fn mexttout(&mut self) -> MEXTTOUT_W<'_>

Bit 8 - Master SCL Low Extend Timeout

pub fn sexttout(&mut self) -> SEXTTOUT_W<'_>

Bit 9 - Slave SCL Low Extend Timeout

pub fn lenerr(&mut self) -> LENERR_W<'_>

Bit 10 - Length Error

impl W<u32, Reg<u32, _ADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:10 - Address Value

pub fn lenen(&mut self) -> LENEN_W<'_>

Bit 13 - Length Enable

pub fn hs(&mut self) -> HS_W<'_>

Bit 14 - High Speed Mode

pub fn tenbiten(&mut self) -> TENBITEN_W<'_>

Bit 15 - Ten Bit Addressing Enable

pub fn len(&mut self) -> LEN_W<'_>

Bits 16:23 - Length

impl W<u8, Reg<u8, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:7 - Data Value

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgstop(&mut self) -> DBGSTOP_W<'_>

Bit 0 - Debug Mode

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:4 - Operating Mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 7 - Run during Standby

pub fn pinout(&mut self) -> PINOUT_W<'_>

Bit 16 - Pin Usage

pub fn sdahold(&mut self) -> SDAHOLD_W<'_>

Bits 20:21 - SDA Hold Time

pub fn sexttoen(&mut self) -> SEXTTOEN_W<'_>

Bit 23 - Slave SCL Low Extend Timeout

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 24:25 - Transfer Speed

pub fn sclsm(&mut self) -> SCLSM_W<'_>

Bit 27 - SCL Clock Stretch Mode

pub fn lowtouten(&mut self) -> LOWTOUTEN_W<'_>

Bit 30 - SCL Low Timeout Enable

impl W<u32, Reg<u32, _CTRLB>>

pub fn smen(&mut self) -> SMEN_W<'_>

Bit 8 - Smart Mode Enable

pub fn gcmd(&mut self) -> GCMD_W<'_>

Bit 9 - PMBus Group Command

pub fn aacken(&mut self) -> AACKEN_W<'_>

Bit 10 - Automatic Address Acknowledge

pub fn amode(&mut self) -> AMODE_W<'_>

Bits 14:15 - Address Mode

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 16:17 - Command

pub fn ackact(&mut self) -> ACKACT_W<'_>

Bit 18 - Acknowledge Action

impl W<u8, Reg<u8, _INTENCLR>>

pub fn prec(&mut self) -> PREC_W<'_>

Bit 0 - Stop Received Interrupt Disable

pub fn amatch(&mut self) -> AMATCH_W<'_>

Bit 1 - Address Match Interrupt Disable

pub fn drdy(&mut self) -> DRDY_W<'_>

Bit 2 - Data Interrupt Disable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn prec(&mut self) -> PREC_W<'_>

Bit 0 - Stop Received Interrupt Enable

pub fn amatch(&mut self) -> AMATCH_W<'_>

Bit 1 - Address Match Interrupt Enable

pub fn drdy(&mut self) -> DRDY_W<'_>

Bit 2 - Data Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn prec(&mut self) -> PREC_W<'_>

Bit 0 - Stop Received Interrupt

pub fn amatch(&mut self) -> AMATCH_W<'_>

Bit 1 - Address Match Interrupt

pub fn drdy(&mut self) -> DRDY_W<'_>

Bit 2 - Data Interrupt

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt

impl W<u16, Reg<u16, _STATUS>>

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 0 - Bus Error

pub fn coll(&mut self) -> COLL_W<'_>

Bit 1 - Transmit Collision

pub fn lowtout(&mut self) -> LOWTOUT_W<'_>

Bit 6 - SCL Low Timeout

pub fn sexttout(&mut self) -> SEXTTOUT_W<'_>

Bit 9 - Slave SCL Low Extend Timeout

pub fn hs(&mut self) -> HS_W<'_>

Bit 10 - High Speed

impl W<u32, Reg<u32, _ADDR>>

pub fn gencen(&mut self) -> GENCEN_W<'_>

Bit 0 - General Call Address Enable

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 1:10 - Address Value

pub fn tenbiten(&mut self) -> TENBITEN_W<'_>

Bit 15 - Ten Bit Addressing Enable

pub fn addrmask(&mut self) -> ADDRMASK_W<'_>

Bits 17:26 - Address Mask

impl W<u8, Reg<u8, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:7 - Data Value

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:4 - Operating Mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 7 - Run during Standby

pub fn ibon(&mut self) -> IBON_W<'_>

Bit 8 - Immediate Buffer Overflow Notification

pub fn dopo(&mut self) -> DOPO_W<'_>

Bits 16:17 - Data Out Pinout

pub fn dipo(&mut self) -> DIPO_W<'_>

Bits 20:21 - Data In Pinout

pub fn form(&mut self) -> FORM_W<'_>

Bits 24:27 - Frame Format

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 28 - Clock Phase

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 29 - Clock Polarity

pub fn dord(&mut self) -> DORD_W<'_>

Bit 30 - Data Order

impl W<u32, Reg<u32, _CTRLB>>

pub fn chsize(&mut self) -> CHSIZE_W<'_>

Bits 0:2 - Character Size

pub fn ploaden(&mut self) -> PLOADEN_W<'_>

Bit 6 - Data Preload Enable

pub fn ssde(&mut self) -> SSDE_W<'_>

Bit 9 - Slave Select Low Detect Enable

pub fn mssen(&mut self) -> MSSEN_W<'_>

Bit 13 - Master Slave Select Enable

pub fn amode(&mut self) -> AMODE_W<'_>

Bits 14:15 - Address Mode

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 17 - Receiver Enable

impl W<u8, Reg<u8, _BAUD>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:7 - Baud Rate Value

impl W<u8, Reg<u8, _INTENCLR>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt Disable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt Disable

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt Disable

pub fn ssl(&mut self) -> SSL_W<'_>

Bit 3 - Slave Select Low Interrupt Disable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt Enable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt Enable

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt Enable

pub fn ssl(&mut self) -> SSL_W<'_>

Bit 3 - Slave Select Low Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt

pub fn ssl(&mut self) -> SSL_W<'_>

Bit 3 - Slave Select Low Interrupt Flag

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt

impl W<u16, Reg<u16, _STATUS>>

pub fn bufovf(&mut self) -> BUFOVF_W<'_>

Bit 2 - Buffer Overflow

impl W<u32, Reg<u32, _ADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:7 - Address Value

pub fn addrmask(&mut self) -> ADDRMASK_W<'_>

Bits 16:23 - Address Mask

impl W<u32, Reg<u32, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:8 - Data Value

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgstop(&mut self) -> DBGSTOP_W<'_>

Bit 0 - Debug Mode

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:4 - Operating Mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 7 - Run during Standby

pub fn ibon(&mut self) -> IBON_W<'_>

Bit 8 - Immediate Buffer Overflow Notification

pub fn sampr(&mut self) -> SAMPR_W<'_>

Bits 13:15 - Sample

pub fn txpo(&mut self) -> TXPO_W<'_>

Bits 16:17 - Transmit Data Pinout

pub fn rxpo(&mut self) -> RXPO_W<'_>

Bits 20:21 - Receive Data Pinout

pub fn sampa(&mut self) -> SAMPA_W<'_>

Bits 22:23 - Sample Adjustment

pub fn form(&mut self) -> FORM_W<'_>

Bits 24:27 - Frame Format

pub fn cmode(&mut self) -> CMODE_W<'_>

Bit 28 - Communication Mode

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 29 - Clock Polarity

pub fn dord(&mut self) -> DORD_W<'_>

Bit 30 - Data Order

impl W<u32, Reg<u32, _CTRLB>>

pub fn chsize(&mut self) -> CHSIZE_W<'_>

Bits 0:2 - Character Size

pub fn sbmode(&mut self) -> SBMODE_W<'_>

Bit 6 - Stop Bit Mode

pub fn colden(&mut self) -> COLDEN_W<'_>

Bit 8 - Collision Detection Enable

pub fn sfde(&mut self) -> SFDE_W<'_>

Bit 9 - Start of Frame Detection Enable

pub fn enc(&mut self) -> ENC_W<'_>

Bit 10 - Encoding Format

pub fn pmode(&mut self) -> PMODE_W<'_>

Bit 13 - Parity Mode

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 16 - Transmitter Enable

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 17 - Receiver Enable

impl W<u16, Reg<u16, _BAUD>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:15 - Baud Rate Value

impl W<u16, Reg<u16, _BAUD_FRAC_MODE>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:12 - Baud Rate Value

pub fn fp(&mut self) -> FP_W<'_>

Bits 13:15 - Fractional Part

impl W<u16, Reg<u16, _BAUD_FRACFP_MODE>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:12 - Baud Rate Value

pub fn fp(&mut self) -> FP_W<'_>

Bits 13:15 - Fractional Part

impl W<u16, Reg<u16, _BAUD_USARTFP_MODE>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:15 - Baud Rate Value

impl W<u8, Reg<u8, _RXPL>>

pub fn rxpl(&mut self) -> RXPL_W<'_>

Bits 0:7 - Receive Pulse Length

impl W<u8, Reg<u8, _INTENCLR>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt Disable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt Disable

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt Disable

pub fn rxs(&mut self) -> RXS_W<'_>

Bit 3 - Receive Start Interrupt Disable

pub fn ctsic(&mut self) -> CTSIC_W<'_>

Bit 4 - Clear To Send Input Change Interrupt Disable

pub fn rxbrk(&mut self) -> RXBRK_W<'_>

Bit 5 - Break Received Interrupt Disable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt Enable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt Enable

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt Enable

pub fn rxs(&mut self) -> RXS_W<'_>

Bit 3 - Receive Start Interrupt Enable

pub fn ctsic(&mut self) -> CTSIC_W<'_>

Bit 4 - Clear To Send Input Change Interrupt Enable

pub fn rxbrk(&mut self) -> RXBRK_W<'_>

Bit 5 - Break Received Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt

pub fn rxs(&mut self) -> RXS_W<'_>

Bit 3 - Receive Start Interrupt

pub fn ctsic(&mut self) -> CTSIC_W<'_>

Bit 4 - Clear To Send Input Change Interrupt

pub fn rxbrk(&mut self) -> RXBRK_W<'_>

Bit 5 - Break Received Interrupt

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt

impl W<u16, Reg<u16, _STATUS>>

pub fn perr(&mut self) -> PERR_W<'_>

Bit 0 - Parity Error

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 1 - Frame Error

pub fn bufovf(&mut self) -> BUFOVF_W<'_>

Bit 2 - Buffer Overflow

pub fn isf(&mut self) -> ISF_W<'_>

Bit 4 - Inconsistent Sync Field

pub fn coll(&mut self) -> COLL_W<'_>

Bit 5 - Collision Detected

impl W<u16, Reg<u16, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:8 - Data Value

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgstop(&mut self) -> DBGSTOP_W<'_>

Bit 0 - Debug Mode

impl W<u32, Reg<u32, _INTENCLR>>

pub fn xoscrdy(&mut self) -> XOSCRDY_W<'_>

Bit 0 - XOSC Ready Interrupt Enable

pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W<'_>

Bit 1 - XOSC32K Ready Interrupt Enable

pub fn osc32krdy(&mut self) -> OSC32KRDY_W<'_>

Bit 2 - OSC32K Ready Interrupt Enable

pub fn osc8mrdy(&mut self) -> OSC8MRDY_W<'_>

Bit 3 - OSC8M Ready Interrupt Enable

pub fn dfllrdy(&mut self) -> DFLLRDY_W<'_>

Bit 4 - DFLL Ready Interrupt Enable

pub fn dflloob(&mut self) -> DFLLOOB_W<'_>

Bit 5 - DFLL Out Of Bounds Interrupt Enable

pub fn dflllckf(&mut self) -> DFLLLCKF_W<'_>

Bit 6 - DFLL Lock Fine Interrupt Enable

pub fn dflllckc(&mut self) -> DFLLLCKC_W<'_>

Bit 7 - DFLL Lock Coarse Interrupt Enable

pub fn dfllrcs(&mut self) -> DFLLRCS_W<'_>

Bit 8 - DFLL Reference Clock Stopped Interrupt Enable

pub fn bod33rdy(&mut self) -> BOD33RDY_W<'_>

Bit 9 - BOD33 Ready Interrupt Enable

pub fn bod33det(&mut self) -> BOD33DET_W<'_>

Bit 10 - BOD33 Detection Interrupt Enable

pub fn b33srdy(&mut self) -> B33SRDY_W<'_>

Bit 11 - BOD33 Synchronization Ready Interrupt Enable

pub fn dplllckr(&mut self) -> DPLLLCKR_W<'_>

Bit 15 - DPLL Lock Rise Interrupt Enable

pub fn dplllckf(&mut self) -> DPLLLCKF_W<'_>

Bit 16 - DPLL Lock Fall Interrupt Enable

pub fn dplllto(&mut self) -> DPLLLTO_W<'_>

Bit 17 - DPLL Lock Timeout Interrupt Enable

impl W<u32, Reg<u32, _INTENSET>>

pub fn xoscrdy(&mut self) -> XOSCRDY_W<'_>

Bit 0 - XOSC Ready Interrupt Enable

pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W<'_>

Bit 1 - XOSC32K Ready Interrupt Enable

pub fn osc32krdy(&mut self) -> OSC32KRDY_W<'_>

Bit 2 - OSC32K Ready Interrupt Enable

pub fn osc8mrdy(&mut self) -> OSC8MRDY_W<'_>

Bit 3 - OSC8M Ready Interrupt Enable

pub fn dfllrdy(&mut self) -> DFLLRDY_W<'_>

Bit 4 - DFLL Ready Interrupt Enable

pub fn dflloob(&mut self) -> DFLLOOB_W<'_>

Bit 5 - DFLL Out Of Bounds Interrupt Enable

pub fn dflllckf(&mut self) -> DFLLLCKF_W<'_>

Bit 6 - DFLL Lock Fine Interrupt Enable

pub fn dflllckc(&mut self) -> DFLLLCKC_W<'_>

Bit 7 - DFLL Lock Coarse Interrupt Enable

pub fn dfllrcs(&mut self) -> DFLLRCS_W<'_>

Bit 8 - DFLL Reference Clock Stopped Interrupt Enable

pub fn bod33rdy(&mut self) -> BOD33RDY_W<'_>

Bit 9 - BOD33 Ready Interrupt Enable

pub fn bod33det(&mut self) -> BOD33DET_W<'_>

Bit 10 - BOD33 Detection Interrupt Enable

pub fn b33srdy(&mut self) -> B33SRDY_W<'_>

Bit 11 - BOD33 Synchronization Ready Interrupt Enable

pub fn dplllckr(&mut self) -> DPLLLCKR_W<'_>

Bit 15 - DPLL Lock Rise Interrupt Enable

pub fn dplllckf(&mut self) -> DPLLLCKF_W<'_>

Bit 16 - DPLL Lock Fall Interrupt Enable

pub fn dplllto(&mut self) -> DPLLLTO_W<'_>

Bit 17 - DPLL Lock Timeout Interrupt Enable

impl W<u32, Reg<u32, _INTFLAG>>

pub fn xoscrdy(&mut self) -> XOSCRDY_W<'_>

Bit 0 - XOSC Ready

pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W<'_>

Bit 1 - XOSC32K Ready

pub fn osc32krdy(&mut self) -> OSC32KRDY_W<'_>

Bit 2 - OSC32K Ready

pub fn osc8mrdy(&mut self) -> OSC8MRDY_W<'_>

Bit 3 - OSC8M Ready

pub fn dfllrdy(&mut self) -> DFLLRDY_W<'_>

Bit 4 - DFLL Ready

pub fn dflloob(&mut self) -> DFLLOOB_W<'_>

Bit 5 - DFLL Out Of Bounds

pub fn dflllckf(&mut self) -> DFLLLCKF_W<'_>

Bit 6 - DFLL Lock Fine

pub fn dflllckc(&mut self) -> DFLLLCKC_W<'_>

Bit 7 - DFLL Lock Coarse

pub fn dfllrcs(&mut self) -> DFLLRCS_W<'_>

Bit 8 - DFLL Reference Clock Stopped

pub fn bod33rdy(&mut self) -> BOD33RDY_W<'_>

Bit 9 - BOD33 Ready

pub fn bod33det(&mut self) -> BOD33DET_W<'_>

Bit 10 - BOD33 Detection

pub fn b33srdy(&mut self) -> B33SRDY_W<'_>

Bit 11 - BOD33 Synchronization Ready

pub fn dplllckr(&mut self) -> DPLLLCKR_W<'_>

Bit 15 - DPLL Lock Rise

pub fn dplllckf(&mut self) -> DPLLLCKF_W<'_>

Bit 16 - DPLL Lock Fall

pub fn dplllto(&mut self) -> DPLLLTO_W<'_>

Bit 17 - DPLL Lock Timeout

impl W<u16, Reg<u16, _XOSC>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Oscillator Enable

pub fn xtalen(&mut self) -> XTALEN_W<'_>

Bit 2 - Crystal Oscillator Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - On Demand Control

pub fn gain(&mut self) -> GAIN_W<'_>

Bits 8:10 - Oscillator Gain

pub fn ampgc(&mut self) -> AMPGC_W<'_>

Bit 11 - Automatic Amplitude Gain Control

pub fn startup(&mut self) -> STARTUP_W<'_>

Bits 12:15 - Start-Up Time

impl W<u16, Reg<u16, _XOSC32K>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Oscillator Enable

pub fn xtalen(&mut self) -> XTALEN_W<'_>

Bit 2 - Crystal Oscillator Enable

pub fn en32k(&mut self) -> EN32K_W<'_>

Bit 3 - 32kHz Output Enable

pub fn en1k(&mut self) -> EN1K_W<'_>

Bit 4 - 1kHz Output Enable

pub fn aampen(&mut self) -> AAMPEN_W<'_>

Bit 5 - Automatic Amplitude Control Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - On Demand Control

pub fn startup(&mut self) -> STARTUP_W<'_>

Bits 8:10 - Oscillator Start-Up Time

pub fn wrtlock(&mut self) -> WRTLOCK_W<'_>

Bit 12 - Write Lock

impl W<u32, Reg<u32, _OSC32K>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Oscillator Enable

pub fn en32k(&mut self) -> EN32K_W<'_>

Bit 2 - 32kHz Output Enable

pub fn en1k(&mut self) -> EN1K_W<'_>

Bit 3 - 1kHz Output Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - On Demand Control

pub fn startup(&mut self) -> STARTUP_W<'_>

Bits 8:10 - Oscillator Start-Up Time

pub fn wrtlock(&mut self) -> WRTLOCK_W<'_>

Bit 12 - Write Lock

pub fn calib(&mut self) -> CALIB_W<'_>

Bits 16:22 - Oscillator Calibration

impl W<u8, Reg<u8, _OSCULP32K>>

pub fn calib(&mut self) -> CALIB_W<'_>

Bits 0:4 - Oscillator Calibration

pub fn wrtlock(&mut self) -> WRTLOCK_W<'_>

Bit 7 - Write Lock

impl W<u32, Reg<u32, _OSC8M>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Oscillator Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - On Demand Control

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:9 - Oscillator Prescaler

pub fn calib(&mut self) -> CALIB_W<'_>

Bits 16:27 - Oscillator Calibration

pub fn frange(&mut self) -> FRANGE_W<'_>

Bits 30:31 - Oscillator Frequency Range

impl W<u16, Reg<u16, _DFLLCTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - DFLL Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bit 2 - Operating Mode Selection

pub fn stable(&mut self) -> STABLE_W<'_>

Bit 3 - Stable DFLL Frequency

pub fn llaw(&mut self) -> LLAW_W<'_>

Bit 4 - Lose Lock After Wake

pub fn usbcrm(&mut self) -> USBCRM_W<'_>

Bit 5 - USB Clock Recovery Mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - On Demand Control

pub fn ccdis(&mut self) -> CCDIS_W<'_>

Bit 8 - Chill Cycle Disable

pub fn qldis(&mut self) -> QLDIS_W<'_>

Bit 9 - Quick Lock Disable

pub fn bplckc(&mut self) -> BPLCKC_W<'_>

Bit 10 - Bypass Coarse Lock

pub fn waitlock(&mut self) -> WAITLOCK_W<'_>

Bit 11 - Wait Lock

impl W<u32, Reg<u32, _DFLLVAL>>

pub fn fine(&mut self) -> FINE_W<'_>

Bits 0:9 - Fine Value

pub fn coarse(&mut self) -> COARSE_W<'_>

Bits 10:15 - Coarse Value

impl W<u32, Reg<u32, _DFLLMUL>>

pub fn mul(&mut self) -> MUL_W<'_>

Bits 0:15 - DFLL Multiply Factor

pub fn fstep(&mut self) -> FSTEP_W<'_>

Bits 16:25 - Fine Maximum Step

pub fn cstep(&mut self) -> CSTEP_W<'_>

Bits 26:31 - Coarse Maximum Step

impl W<u8, Reg<u8, _DFLLSYNC>>

pub fn readreq(&mut self) -> READREQ_W<'_>

Bit 7 - Read Request

impl W<u32, Reg<u32, _BOD33>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn hyst(&mut self) -> HYST_W<'_>

Bit 2 - Hysteresis

pub fn action(&mut self) -> ACTION_W<'_>

Bits 3:4 - BOD33 Action

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn mode(&mut self) -> MODE_W<'_>

Bit 8 - Operation Mode

pub fn cen(&mut self) -> CEN_W<'_>

Bit 9 - Clock Enable

pub fn psel(&mut self) -> PSEL_W<'_>

Bits 12:15 - Prescaler Select

pub fn level(&mut self) -> LEVEL_W<'_>

Bits 16:21 - BOD33 Threshold Level

impl W<u32, Reg<u32, _VREF>>

pub fn tsen(&mut self) -> TSEN_W<'_>

Bit 1 - Temperature Sensor Enable

pub fn bgouten(&mut self) -> BGOUTEN_W<'_>

Bit 2 - Bandgap Output Enable

pub fn calib(&mut self) -> CALIB_W<'_>

Bits 16:26 - Bandgap Voltage Generator Calibration

impl W<u8, Reg<u8, _DPLLCTRLA>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - DPLL Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - On Demand Clock Activation

impl W<u32, Reg<u32, _DPLLRATIO>>

pub fn ldr(&mut self) -> LDR_W<'_>

Bits 0:11 - Loop Divider Ratio

pub fn ldrfrac(&mut self) -> LDRFRAC_W<'_>

Bits 16:19 - Loop Divider Ratio Fractional Part

impl W<u32, Reg<u32, _DPLLCTRLB>>

pub fn filter(&mut self) -> FILTER_W<'_>

Bits 0:1 - Proportional Integral Filter Selection

pub fn lpen(&mut self) -> LPEN_W<'_>

Bit 2 - Low-Power Enable

pub fn wuf(&mut self) -> WUF_W<'_>

Bit 3 - Wake Up Fast

pub fn refclk(&mut self) -> REFCLK_W<'_>

Bits 4:5 - Reference Clock Selection

pub fn ltime(&mut self) -> LTIME_W<'_>

Bits 8:10 - Lock Time

pub fn lbypass(&mut self) -> LBYPASS_W<'_>

Bit 12 - Lock Bypass

pub fn div(&mut self) -> DIV_W<'_>

Bits 16:26 - Clock Divider

impl W<u16, Reg<u16, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - TC Mode

pub fn wavegen(&mut self) -> WAVEGEN_W<'_>

Bits 5:6 - Waveform Generation Operation

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:10 - Prescaler

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 11 - Run in Standby

pub fn prescsync(&mut self) -> PRESCSYNC_W<'_>

Bits 12:13 - Prescaler and Counter Synchronization

impl W<u16, Reg<u16, _READREQ>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:4 - Address

pub fn rcont(&mut self) -> RCONT_W<'_>

Bit 14 - Read Continuously

pub fn rreq(&mut self) -> RREQ_W<'_>

Bit 15 - Read Request

impl W<u8, Reg<u8, _CTRLBCLR>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 6:7 - Command

impl W<u8, Reg<u8, _CTRLBSET>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 6:7 - Command

impl W<u8, Reg<u8, _CTRLC>>

pub fn inven0(&mut self) -> INVEN0_W<'_>

Bit 0 - Output Waveform 0 Invert Enable

pub fn inven1(&mut self) -> INVEN1_W<'_>

Bit 1 - Output Waveform 1 Invert Enable

pub fn cpten0(&mut self) -> CPTEN0_W<'_>

Bit 4 - Capture Channel 0 Enable

pub fn cpten1(&mut self) -> CPTEN1_W<'_>

Bit 5 - Capture Channel 1 Enable

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Run Mode

impl W<u16, Reg<u16, _EVCTRL>>

pub fn evact(&mut self) -> EVACT_W<'_>

Bits 0:2 - Event Action

pub fn tcinv(&mut self) -> TCINV_W<'_>

Bit 4 - TC Inverted Event Input

pub fn tcei(&mut self) -> TCEI_W<'_>

Bit 5 - TC Event Input

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 8 - Overflow/Underflow Event Output Enable

pub fn mceo0(&mut self) -> MCEO0_W<'_>

Bit 12 - Match or Capture Channel 0 Event Output Enable

pub fn mceo1(&mut self) -> MCEO1_W<'_>

Bit 13 - Match or Capture Channel 1 Event Output Enable

impl W<u8, Reg<u8, _INTENCLR>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - Error Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 3 - Synchronization Ready Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - Match or Capture Channel 0 Interrupt Enable

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - Match or Capture Channel 1 Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - Error Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 3 - Synchronization Ready Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - Match or Capture Channel 0 Interrupt Enable

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - Match or Capture Channel 1 Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - Error

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 3 - Synchronization Ready

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - Match or Capture Channel 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - Match or Capture Channel 1

impl W<u8, Reg<u8, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:7 - Counter Value

impl W<u8, Reg<u8, _PER>>

pub fn per(&mut self) -> PER_W<'_>

Bits 0:7 - Period Value

impl W<u8, Reg<u8, _CC>>

pub fn cc(&mut self) -> CC_W<'_>

Bits 0:7 - Compare/Capture Value

impl W<u16, Reg<u16, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - TC Mode

pub fn wavegen(&mut self) -> WAVEGEN_W<'_>

Bits 5:6 - Waveform Generation Operation

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:10 - Prescaler

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 11 - Run in Standby

pub fn prescsync(&mut self) -> PRESCSYNC_W<'_>

Bits 12:13 - Prescaler and Counter Synchronization

impl W<u16, Reg<u16, _READREQ>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:4 - Address

pub fn rcont(&mut self) -> RCONT_W<'_>

Bit 14 - Read Continuously

pub fn rreq(&mut self) -> RREQ_W<'_>

Bit 15 - Read Request

impl W<u8, Reg<u8, _CTRLBCLR>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 6:7 - Command

impl W<u8, Reg<u8, _CTRLBSET>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 6:7 - Command

impl W<u8, Reg<u8, _CTRLC>>

pub fn inven0(&mut self) -> INVEN0_W<'_>

Bit 0 - Output Waveform 0 Invert Enable

pub fn inven1(&mut self) -> INVEN1_W<'_>

Bit 1 - Output Waveform 1 Invert Enable

pub fn cpten0(&mut self) -> CPTEN0_W<'_>

Bit 4 - Capture Channel 0 Enable

pub fn cpten1(&mut self) -> CPTEN1_W<'_>

Bit 5 - Capture Channel 1 Enable

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Run Mode

impl W<u16, Reg<u16, _EVCTRL>>

pub fn evact(&mut self) -> EVACT_W<'_>

Bits 0:2 - Event Action

pub fn tcinv(&mut self) -> TCINV_W<'_>

Bit 4 - TC Inverted Event Input

pub fn tcei(&mut self) -> TCEI_W<'_>

Bit 5 - TC Event Input

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 8 - Overflow/Underflow Event Output Enable

pub fn mceo0(&mut self) -> MCEO0_W<'_>

Bit 12 - Match or Capture Channel 0 Event Output Enable

pub fn mceo1(&mut self) -> MCEO1_W<'_>

Bit 13 - Match or Capture Channel 1 Event Output Enable

impl W<u8, Reg<u8, _INTENCLR>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - Error Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 3 - Synchronization Ready Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - Match or Capture Channel 0 Interrupt Enable

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - Match or Capture Channel 1 Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - Error Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 3 - Synchronization Ready Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - Match or Capture Channel 0 Interrupt Enable

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - Match or Capture Channel 1 Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - Error

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 3 - Synchronization Ready

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - Match or Capture Channel 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - Match or Capture Channel 1

impl W<u16, Reg<u16, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Count Value

impl W<u16, Reg<u16, _CC>>

pub fn cc(&mut self) -> CC_W<'_>

Bits 0:15 - Compare/Capture Value

impl W<u16, Reg<u16, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - TC Mode

pub fn wavegen(&mut self) -> WAVEGEN_W<'_>

Bits 5:6 - Waveform Generation Operation

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:10 - Prescaler

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 11 - Run in Standby

pub fn prescsync(&mut self) -> PRESCSYNC_W<'_>

Bits 12:13 - Prescaler and Counter Synchronization

impl W<u16, Reg<u16, _READREQ>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:4 - Address

pub fn rcont(&mut self) -> RCONT_W<'_>

Bit 14 - Read Continuously

pub fn rreq(&mut self) -> RREQ_W<'_>

Bit 15 - Read Request

impl W<u8, Reg<u8, _CTRLBCLR>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 6:7 - Command

impl W<u8, Reg<u8, _CTRLBSET>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 6:7 - Command

impl W<u8, Reg<u8, _CTRLC>>

pub fn inven0(&mut self) -> INVEN0_W<'_>

Bit 0 - Output Waveform 0 Invert Enable

pub fn inven1(&mut self) -> INVEN1_W<'_>

Bit 1 - Output Waveform 1 Invert Enable

pub fn cpten0(&mut self) -> CPTEN0_W<'_>

Bit 4 - Capture Channel 0 Enable

pub fn cpten1(&mut self) -> CPTEN1_W<'_>

Bit 5 - Capture Channel 1 Enable

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Run Mode

impl W<u16, Reg<u16, _EVCTRL>>

pub fn evact(&mut self) -> EVACT_W<'_>

Bits 0:2 - Event Action

pub fn tcinv(&mut self) -> TCINV_W<'_>

Bit 4 - TC Inverted Event Input

pub fn tcei(&mut self) -> TCEI_W<'_>

Bit 5 - TC Event Input

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 8 - Overflow/Underflow Event Output Enable

pub fn mceo0(&mut self) -> MCEO0_W<'_>

Bit 12 - Match or Capture Channel 0 Event Output Enable

pub fn mceo1(&mut self) -> MCEO1_W<'_>

Bit 13 - Match or Capture Channel 1 Event Output Enable

impl W<u8, Reg<u8, _INTENCLR>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - Error Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 3 - Synchronization Ready Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - Match or Capture Channel 0 Interrupt Enable

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - Match or Capture Channel 1 Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - Error Interrupt Enable

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 3 - Synchronization Ready Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - Match or Capture Channel 0 Interrupt Enable

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - Match or Capture Channel 1 Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - Error

pub fn syncrdy(&mut self) -> SYNCRDY_W<'_>

Bit 3 - Synchronization Ready

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - Match or Capture Channel 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - Match or Capture Channel 1

impl W<u32, Reg<u32, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Count Value

impl W<u32, Reg<u32, _CC>>

pub fn cc(&mut self) -> CC_W<'_>

Bits 0:31 - Compare/Capture Value

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn resolution(&mut self) -> RESOLUTION_W<'_>

Bits 5:6 - Enhanced Resolution

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:10 - Prescaler

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 11 - Run in Standby

pub fn prescsync(&mut self) -> PRESCSYNC_W<'_>

Bits 12:13 - Prescaler and Counter Synchronization Selection

pub fn alock(&mut self) -> ALOCK_W<'_>

Bit 14 - Auto Lock

pub fn cpten0(&mut self) -> CPTEN0_W<'_>

Bit 24 - Capture Channel 0 Enable

pub fn cpten1(&mut self) -> CPTEN1_W<'_>

Bit 25 - Capture Channel 1 Enable

pub fn cpten2(&mut self) -> CPTEN2_W<'_>

Bit 26 - Capture Channel 2 Enable

pub fn cpten3(&mut self) -> CPTEN3_W<'_>

Bit 27 - Capture Channel 3 Enable

impl W<u8, Reg<u8, _CTRLBCLR>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn lupd(&mut self) -> LUPD_W<'_>

Bit 1 - Lock Update

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot

pub fn idxcmd(&mut self) -> IDXCMD_W<'_>

Bits 3:4 - Ramp Index Command

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 5:7 - TCC Command

impl W<u8, Reg<u8, _CTRLBSET>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn lupd(&mut self) -> LUPD_W<'_>

Bit 1 - Lock Update

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot

pub fn idxcmd(&mut self) -> IDXCMD_W<'_>

Bits 3:4 - Ramp Index Command

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 5:7 - TCC Command

impl W<u32, Reg<u32, _FCTRLA>>

pub fn src(&mut self) -> SRC_W<'_>

Bits 0:1 - Fault A Source

pub fn keep(&mut self) -> KEEP_W<'_>

Bit 3 - Fault A Keeper

pub fn qual(&mut self) -> QUAL_W<'_>

Bit 4 - Fault A Qualification

pub fn blank(&mut self) -> BLANK_W<'_>

Bits 5:6 - Fault A Blanking Mode

pub fn restart(&mut self) -> RESTART_W<'_>

Bit 7 - Fault A Restart

pub fn halt(&mut self) -> HALT_W<'_>

Bits 8:9 - Fault A Halt Mode

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 10:11 - Fault A Capture Channel

pub fn capture(&mut self) -> CAPTURE_W<'_>

Bits 12:14 - Fault A Capture Action

pub fn blankpresc(&mut self) -> BLANKPRESC_W<'_>

Bit 15 - Fault A Blanking Prescaler

pub fn blankval(&mut self) -> BLANKVAL_W<'_>

Bits 16:23 - Fault A Blanking Time

pub fn filterval(&mut self) -> FILTERVAL_W<'_>

Bits 24:27 - Fault A Filter Value

impl W<u32, Reg<u32, _FCTRLB>>

pub fn src(&mut self) -> SRC_W<'_>

Bits 0:1 - Fault B Source

pub fn keep(&mut self) -> KEEP_W<'_>

Bit 3 - Fault B Keeper

pub fn qual(&mut self) -> QUAL_W<'_>

Bit 4 - Fault B Qualification

pub fn blank(&mut self) -> BLANK_W<'_>

Bits 5:6 - Fault B Blanking Mode

pub fn restart(&mut self) -> RESTART_W<'_>

Bit 7 - Fault B Restart

pub fn halt(&mut self) -> HALT_W<'_>

Bits 8:9 - Fault B Halt Mode

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 10:11 - Fault B Capture Channel

pub fn capture(&mut self) -> CAPTURE_W<'_>

Bits 12:14 - Fault B Capture Action

pub fn blankpresc(&mut self) -> BLANKPRESC_W<'_>

Bit 15 - Fault B Blanking Prescaler

pub fn blankval(&mut self) -> BLANKVAL_W<'_>

Bits 16:23 - Fault B Blanking Time

pub fn filterval(&mut self) -> FILTERVAL_W<'_>

Bits 24:27 - Fault B Filter Value

impl W<u32, Reg<u32, _WEXCTRL>>

pub fn otmx(&mut self) -> OTMX_W<'_>

Bits 0:1 - Output Matrix

pub fn dtien0(&mut self) -> DTIEN0_W<'_>

Bit 8 - Dead-time Insertion Generator 0 Enable

pub fn dtien1(&mut self) -> DTIEN1_W<'_>

Bit 9 - Dead-time Insertion Generator 1 Enable

pub fn dtien2(&mut self) -> DTIEN2_W<'_>

Bit 10 - Dead-time Insertion Generator 2 Enable

pub fn dtien3(&mut self) -> DTIEN3_W<'_>

Bit 11 - Dead-time Insertion Generator 3 Enable

pub fn dtls(&mut self) -> DTLS_W<'_>

Bits 16:23 - Dead-time Low Side Outputs Value

pub fn dths(&mut self) -> DTHS_W<'_>

Bits 24:31 - Dead-time High Side Outputs Value

impl W<u32, Reg<u32, _DRVCTRL>>

pub fn nre0(&mut self) -> NRE0_W<'_>

Bit 0 - Non-Recoverable State 0 Output Enable

pub fn nre1(&mut self) -> NRE1_W<'_>

Bit 1 - Non-Recoverable State 1 Output Enable

pub fn nre2(&mut self) -> NRE2_W<'_>

Bit 2 - Non-Recoverable State 2 Output Enable

pub fn nre3(&mut self) -> NRE3_W<'_>

Bit 3 - Non-Recoverable State 3 Output Enable

pub fn nre4(&mut self) -> NRE4_W<'_>

Bit 4 - Non-Recoverable State 4 Output Enable

pub fn nre5(&mut self) -> NRE5_W<'_>

Bit 5 - Non-Recoverable State 5 Output Enable

pub fn nre6(&mut self) -> NRE6_W<'_>

Bit 6 - Non-Recoverable State 6 Output Enable

pub fn nre7(&mut self) -> NRE7_W<'_>

Bit 7 - Non-Recoverable State 7 Output Enable

pub fn nrv0(&mut self) -> NRV0_W<'_>

Bit 8 - Non-Recoverable State 0 Output Value

pub fn nrv1(&mut self) -> NRV1_W<'_>

Bit 9 - Non-Recoverable State 1 Output Value

pub fn nrv2(&mut self) -> NRV2_W<'_>

Bit 10 - Non-Recoverable State 2 Output Value

pub fn nrv3(&mut self) -> NRV3_W<'_>

Bit 11 - Non-Recoverable State 3 Output Value

pub fn nrv4(&mut self) -> NRV4_W<'_>

Bit 12 - Non-Recoverable State 4 Output Value

pub fn nrv5(&mut self) -> NRV5_W<'_>

Bit 13 - Non-Recoverable State 5 Output Value

pub fn nrv6(&mut self) -> NRV6_W<'_>

Bit 14 - Non-Recoverable State 6 Output Value

pub fn nrv7(&mut self) -> NRV7_W<'_>

Bit 15 - Non-Recoverable State 7 Output Value

pub fn inven0(&mut self) -> INVEN0_W<'_>

Bit 16 - Output Waveform 0 Inversion

pub fn inven1(&mut self) -> INVEN1_W<'_>

Bit 17 - Output Waveform 1 Inversion

pub fn inven2(&mut self) -> INVEN2_W<'_>

Bit 18 - Output Waveform 2 Inversion

pub fn inven3(&mut self) -> INVEN3_W<'_>

Bit 19 - Output Waveform 3 Inversion

pub fn inven4(&mut self) -> INVEN4_W<'_>

Bit 20 - Output Waveform 4 Inversion

pub fn inven5(&mut self) -> INVEN5_W<'_>

Bit 21 - Output Waveform 5 Inversion

pub fn inven6(&mut self) -> INVEN6_W<'_>

Bit 22 - Output Waveform 6 Inversion

pub fn inven7(&mut self) -> INVEN7_W<'_>

Bit 23 - Output Waveform 7 Inversion

pub fn filterval0(&mut self) -> FILTERVAL0_W<'_>

Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value

pub fn filterval1(&mut self) -> FILTERVAL1_W<'_>

Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Running Mode

pub fn fddbd(&mut self) -> FDDBD_W<'_>

Bit 2 - Fault Detection on Debug Break Detection

impl W<u32, Reg<u32, _EVCTRL>>

pub fn evact0(&mut self) -> EVACT0_W<'_>

Bits 0:2 - Timer/counter Input Event0 Action

pub fn evact1(&mut self) -> EVACT1_W<'_>

Bits 3:5 - Timer/counter Input Event1 Action

pub fn cntsel(&mut self) -> CNTSEL_W<'_>

Bits 6:7 - Timer/counter Output Event Mode

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 8 - Overflow/Underflow Output Event Enable

pub fn trgeo(&mut self) -> TRGEO_W<'_>

Bit 9 - Retrigger Output Event Enable

pub fn cnteo(&mut self) -> CNTEO_W<'_>

Bit 10 - Timer/counter Output Event Enable

pub fn tcinv0(&mut self) -> TCINV0_W<'_>

Bit 12 - Inverted Event 0 Input Enable

pub fn tcinv1(&mut self) -> TCINV1_W<'_>

Bit 13 - Inverted Event 1 Input Enable

pub fn tcei0(&mut self) -> TCEI0_W<'_>

Bit 14 - Timer/counter Event 0 Input Enable

pub fn tcei1(&mut self) -> TCEI1_W<'_>

Bit 15 - Timer/counter Event 1 Input Enable

pub fn mcei0(&mut self) -> MCEI0_W<'_>

Bit 16 - Match or Capture Channel 0 Event Input Enable

pub fn mcei1(&mut self) -> MCEI1_W<'_>

Bit 17 - Match or Capture Channel 1 Event Input Enable

pub fn mcei2(&mut self) -> MCEI2_W<'_>

Bit 18 - Match or Capture Channel 2 Event Input Enable

pub fn mcei3(&mut self) -> MCEI3_W<'_>

Bit 19 - Match or Capture Channel 3 Event Input Enable

pub fn mceo0(&mut self) -> MCEO0_W<'_>

Bit 24 - Match or Capture Channel 0 Event Output Enable

pub fn mceo1(&mut self) -> MCEO1_W<'_>

Bit 25 - Match or Capture Channel 1 Event Output Enable

pub fn mceo2(&mut self) -> MCEO2_W<'_>

Bit 26 - Match or Capture Channel 2 Event Output Enable

pub fn mceo3(&mut self) -> MCEO3_W<'_>

Bit 27 - Match or Capture Channel 3 Event Output Enable

impl W<u32, Reg<u32, _INTENCLR>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow Interrupt Enable

pub fn trg(&mut self) -> TRG_W<'_>

Bit 1 - Retrigger Interrupt Enable

pub fn cnt(&mut self) -> CNT_W<'_>

Bit 2 - Counter Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 3 - Error Interrupt Enable

pub fn dfs(&mut self) -> DFS_W<'_>

Bit 11 - Non-Recoverable Debug Fault Interrupt Enable

pub fn faulta(&mut self) -> FAULTA_W<'_>

Bit 12 - Recoverable Fault A Interrupt Enable

pub fn faultb(&mut self) -> FAULTB_W<'_>

Bit 13 - Recoverable Fault B Interrupt Enable

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 14 - Non-Recoverable Fault 0 Interrupt Enable

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 15 - Non-Recoverable Fault 1 Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 16 - Match or Capture Channel 0 Interrupt Enable

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 17 - Match or Capture Channel 1 Interrupt Enable

pub fn mc2(&mut self) -> MC2_W<'_>

Bit 18 - Match or Capture Channel 2 Interrupt Enable

pub fn mc3(&mut self) -> MC3_W<'_>

Bit 19 - Match or Capture Channel 3 Interrupt Enable

impl W<u32, Reg<u32, _INTENSET>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow Interrupt Enable

pub fn trg(&mut self) -> TRG_W<'_>

Bit 1 - Retrigger Interrupt Enable

pub fn cnt(&mut self) -> CNT_W<'_>

Bit 2 - Counter Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 3 - Error Interrupt Enable

pub fn dfs(&mut self) -> DFS_W<'_>

Bit 11 - Non-Recoverable Debug Fault Interrupt Enable

pub fn faulta(&mut self) -> FAULTA_W<'_>

Bit 12 - Recoverable Fault A Interrupt Enable

pub fn faultb(&mut self) -> FAULTB_W<'_>

Bit 13 - Recoverable Fault B Interrupt Enable

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 14 - Non-Recoverable Fault 0 Interrupt Enable

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 15 - Non-Recoverable Fault 1 Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 16 - Match or Capture Channel 0 Interrupt Enable

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 17 - Match or Capture Channel 1 Interrupt Enable

pub fn mc2(&mut self) -> MC2_W<'_>

Bit 18 - Match or Capture Channel 2 Interrupt Enable

pub fn mc3(&mut self) -> MC3_W<'_>

Bit 19 - Match or Capture Channel 3 Interrupt Enable

impl W<u32, Reg<u32, _INTFLAG>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow

pub fn trg(&mut self) -> TRG_W<'_>

Bit 1 - Retrigger

pub fn cnt(&mut self) -> CNT_W<'_>

Bit 2 - Counter

pub fn err(&mut self) -> ERR_W<'_>

Bit 3 - Error

pub fn dfs(&mut self) -> DFS_W<'_>

Bit 11 - Non-Recoverable Debug Fault

pub fn faulta(&mut self) -> FAULTA_W<'_>

Bit 12 - Recoverable Fault A

pub fn faultb(&mut self) -> FAULTB_W<'_>

Bit 13 - Recoverable Fault B

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 14 - Non-Recoverable Fault 0

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 15 - Non-Recoverable Fault 1

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 16 - Match or Capture 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 17 - Match or Capture 1

pub fn mc2(&mut self) -> MC2_W<'_>

Bit 18 - Match or Capture 2

pub fn mc3(&mut self) -> MC3_W<'_>

Bit 19 - Match or Capture 3

impl W<u32, Reg<u32, _STATUS>>

pub fn dfs(&mut self) -> DFS_W<'_>

Bit 3 - Non-Recoverable Debug Fault State

pub fn pattbv(&mut self) -> PATTBV_W<'_>

Bit 5 - Pattern Buffer Valid

pub fn wavebv(&mut self) -> WAVEBV_W<'_>

Bit 6 - Wave Buffer Valid

pub fn perbv(&mut self) -> PERBV_W<'_>

Bit 7 - Period Buffer Valid

pub fn faulta(&mut self) -> FAULTA_W<'_>

Bit 12 - Recoverable Fault A State

pub fn faultb(&mut self) -> FAULTB_W<'_>

Bit 13 - Recoverable Fault B State

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 14 - Non-Recoverable Fault 0 State

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 15 - Non-Recoverable Fault 1 State

pub fn ccbv0(&mut self) -> CCBV0_W<'_>

Bit 16 - Compare Channel 0 Buffer Valid

pub fn ccbv1(&mut self) -> CCBV1_W<'_>

Bit 17 - Compare Channel 1 Buffer Valid

pub fn ccbv2(&mut self) -> CCBV2_W<'_>

Bit 18 - Compare Channel 2 Buffer Valid

pub fn ccbv3(&mut self) -> CCBV3_W<'_>

Bit 19 - Compare Channel 3 Buffer Valid

impl W<u32, Reg<u32, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:23 - Counter Value

impl W<u32, Reg<u32, _COUNT_DITH4>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 4:23 - Counter Value

impl W<u32, Reg<u32, _COUNT_DITH5>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 5:23 - Counter Value

impl W<u32, Reg<u32, _COUNT_DITH6>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 6:23 - Counter Value

impl W<u16, Reg<u16, _PATT>>

pub fn pge0(&mut self) -> PGE0_W<'_>

Bit 0 - Pattern Generator 0 Output Enable

pub fn pge1(&mut self) -> PGE1_W<'_>

Bit 1 - Pattern Generator 1 Output Enable

pub fn pge2(&mut self) -> PGE2_W<'_>

Bit 2 - Pattern Generator 2 Output Enable

pub fn pge3(&mut self) -> PGE3_W<'_>

Bit 3 - Pattern Generator 3 Output Enable

pub fn pge4(&mut self) -> PGE4_W<'_>

Bit 4 - Pattern Generator 4 Output Enable

pub fn pge5(&mut self) -> PGE5_W<'_>

Bit 5 - Pattern Generator 5 Output Enable

pub fn pge6(&mut self) -> PGE6_W<'_>

Bit 6 - Pattern Generator 6 Output Enable

pub fn pge7(&mut self) -> PGE7_W<'_>

Bit 7 - Pattern Generator 7 Output Enable

pub fn pgv0(&mut self) -> PGV0_W<'_>

Bit 8 - Pattern Generator 0 Output Value

pub fn pgv1(&mut self) -> PGV1_W<'_>

Bit 9 - Pattern Generator 1 Output Value

pub fn pgv2(&mut self) -> PGV2_W<'_>

Bit 10 - Pattern Generator 2 Output Value

pub fn pgv3(&mut self) -> PGV3_W<'_>

Bit 11 - Pattern Generator 3 Output Value

pub fn pgv4(&mut self) -> PGV4_W<'_>

Bit 12 - Pattern Generator 4 Output Value

pub fn pgv5(&mut self) -> PGV5_W<'_>

Bit 13 - Pattern Generator 5 Output Value

pub fn pgv6(&mut self) -> PGV6_W<'_>

Bit 14 - Pattern Generator 6 Output Value

pub fn pgv7(&mut self) -> PGV7_W<'_>

Bit 15 - Pattern Generator 7 Output Value

impl W<u32, Reg<u32, _WAVE>>

pub fn wavegen(&mut self) -> WAVEGEN_W<'_>

Bits 0:2 - Waveform Generation

pub fn ramp(&mut self) -> RAMP_W<'_>

Bits 4:5 - Ramp Mode

pub fn ciperen(&mut self) -> CIPEREN_W<'_>

Bit 7 - Circular period Enable

pub fn ciccen0(&mut self) -> CICCEN0_W<'_>

Bit 8 - Circular Channel 0 Enable

pub fn ciccen1(&mut self) -> CICCEN1_W<'_>

Bit 9 - Circular Channel 1 Enable

pub fn ciccen2(&mut self) -> CICCEN2_W<'_>

Bit 10 - Circular Channel 2 Enable

pub fn ciccen3(&mut self) -> CICCEN3_W<'_>

Bit 11 - Circular Channel 3 Enable

pub fn pol0(&mut self) -> POL0_W<'_>

Bit 16 - Channel 0 Polarity

pub fn pol1(&mut self) -> POL1_W<'_>

Bit 17 - Channel 1 Polarity

pub fn pol2(&mut self) -> POL2_W<'_>

Bit 18 - Channel 2 Polarity

pub fn pol3(&mut self) -> POL3_W<'_>

Bit 19 - Channel 3 Polarity

pub fn swap0(&mut self) -> SWAP0_W<'_>

Bit 24 - Swap DTI Output Pair 0

pub fn swap1(&mut self) -> SWAP1_W<'_>

Bit 25 - Swap DTI Output Pair 1

pub fn swap2(&mut self) -> SWAP2_W<'_>

Bit 26 - Swap DTI Output Pair 2

pub fn swap3(&mut self) -> SWAP3_W<'_>

Bit 27 - Swap DTI Output Pair 3

impl W<u32, Reg<u32, _PER>>

pub fn per(&mut self) -> PER_W<'_>

Bits 0:23 - Period Value

impl W<u32, Reg<u32, _PER_DITH4>>

pub fn dithercy(&mut self) -> DITHERCY_W<'_>

Bits 0:3 - Dithering Cycle Number

pub fn per(&mut self) -> PER_W<'_>

Bits 4:23 - Period Value

impl W<u32, Reg<u32, _PER_DITH5>>

pub fn dithercy(&mut self) -> DITHERCY_W<'_>

Bits 0:4 - Dithering Cycle Number

pub fn per(&mut self) -> PER_W<'_>

Bits 5:23 - Period Value

impl W<u32, Reg<u32, _PER_DITH6>>

pub fn dithercy(&mut self) -> DITHERCY_W<'_>

Bits 0:5 - Dithering Cycle Number

pub fn per(&mut self) -> PER_W<'_>

Bits 6:23 - Period Value

impl W<u32, Reg<u32, _CC>>

pub fn cc(&mut self) -> CC_W<'_>

Bits 0:23 - Channel Compare/Capture Value

impl W<u32, Reg<u32, _CC_DITH4>>

pub fn dithercy(&mut self) -> DITHERCY_W<'_>

Bits 0:3 - Dithering Cycle Number

pub fn cc(&mut self) -> CC_W<'_>

Bits 4:23 - Channel Compare/Capture Value

impl W<u32, Reg<u32, _CC_DITH5>>

pub fn dithercy(&mut self) -> DITHERCY_W<'_>

Bits 0:4 - Dithering Cycle Number

pub fn cc(&mut self) -> CC_W<'_>

Bits 5:23 - Channel Compare/Capture Value

impl W<u32, Reg<u32, _CC_DITH6>>

pub fn dithercy(&mut self) -> DITHERCY_W<'_>

Bits 0:5 - Dithering Cycle Number

pub fn cc(&mut self) -> CC_W<'_>

Bits 6:23 - Channel Compare/Capture Value

impl W<u16, Reg<u16, _PATTB>>

pub fn pgeb0(&mut self) -> PGEB0_W<'_>

Bit 0 - Pattern Generator 0 Output Enable Buffer

pub fn pgeb1(&mut self) -> PGEB1_W<'_>

Bit 1 - Pattern Generator 1 Output Enable Buffer

pub fn pgeb2(&mut self) -> PGEB2_W<'_>

Bit 2 - Pattern Generator 2 Output Enable Buffer

pub fn pgeb3(&mut self) -> PGEB3_W<'_>

Bit 3 - Pattern Generator 3 Output Enable Buffer

pub fn pgeb4(&mut self) -> PGEB4_W<'_>

Bit 4 - Pattern Generator 4 Output Enable Buffer

pub fn pgeb5(&mut self) -> PGEB5_W<'_>

Bit 5 - Pattern Generator 5 Output Enable Buffer

pub fn pgeb6(&mut self) -> PGEB6_W<'_>

Bit 6 - Pattern Generator 6 Output Enable Buffer

pub fn pgeb7(&mut self) -> PGEB7_W<'_>

Bit 7 - Pattern Generator 7 Output Enable Buffer

pub fn pgvb0(&mut self) -> PGVB0_W<'_>

Bit 8 - Pattern Generator 0 Output Enable

pub fn pgvb1(&mut self) -> PGVB1_W<'_>

Bit 9 - Pattern Generator 1 Output Enable

pub fn pgvb2(&mut self) -> PGVB2_W<'_>

Bit 10 - Pattern Generator 2 Output Enable

pub fn pgvb3(&mut self) -> PGVB3_W<'_>

Bit 11 - Pattern Generator 3 Output Enable

pub fn pgvb4(&mut self) -> PGVB4_W<'_>

Bit 12 - Pattern Generator 4 Output Enable

pub fn pgvb5(&mut self) -> PGVB5_W<'_>

Bit 13 - Pattern Generator 5 Output Enable

pub fn pgvb6(&mut self) -> PGVB6_W<'_>

Bit 14 - Pattern Generator 6 Output Enable

pub fn pgvb7(&mut self) -> PGVB7_W<'_>

Bit 15 - Pattern Generator 7 Output Enable

impl W<u32, Reg<u32, _WAVEB>>

pub fn wavegenb(&mut self) -> WAVEGENB_W<'_>

Bits 0:2 - Waveform Generation Buffer

pub fn rampb(&mut self) -> RAMPB_W<'_>

Bits 4:5 - Ramp Mode Buffer

pub fn ciperenb(&mut self) -> CIPERENB_W<'_>

Bit 7 - Circular Period Enable Buffer

pub fn ciccenb0(&mut self) -> CICCENB0_W<'_>

Bit 8 - Circular Channel 0 Enable Buffer

pub fn ciccenb1(&mut self) -> CICCENB1_W<'_>

Bit 9 - Circular Channel 1 Enable Buffer

pub fn ciccenb2(&mut self) -> CICCENB2_W<'_>

Bit 10 - Circular Channel 2 Enable Buffer

pub fn ciccenb3(&mut self) -> CICCENB3_W<'_>

Bit 11 - Circular Channel 3 Enable Buffer

pub fn polb0(&mut self) -> POLB0_W<'_>

Bit 16 - Channel 0 Polarity Buffer

pub fn polb1(&mut self) -> POLB1_W<'_>

Bit 17 - Channel 1 Polarity Buffer

pub fn polb2(&mut self) -> POLB2_W<'_>

Bit 18 - Channel 2 Polarity Buffer

pub fn polb3(&mut self) -> POLB3_W<'_>

Bit 19 - Channel 3 Polarity Buffer

pub fn swapb0(&mut self) -> SWAPB0_W<'_>

Bit 24 - Swap DTI Output Pair 0 Buffer

pub fn swapb1(&mut self) -> SWAPB1_W<'_>

Bit 25 - Swap DTI Output Pair 1 Buffer

pub fn swapb2(&mut self) -> SWAPB2_W<'_>

Bit 26 - Swap DTI Output Pair 2 Buffer

pub fn swapb3(&mut self) -> SWAPB3_W<'_>

Bit 27 - Swap DTI Output Pair 3 Buffer

impl W<u32, Reg<u32, _PERB>>

pub fn perb(&mut self) -> PERB_W<'_>

Bits 0:23 - Period Buffer Value

impl W<u32, Reg<u32, _PERB_DITH4>>

pub fn dithercyb(&mut self) -> DITHERCYB_W<'_>

Bits 0:3 - Dithering Buffer Cycle Number

pub fn perb(&mut self) -> PERB_W<'_>

Bits 4:23 - Period Buffer Value

impl W<u32, Reg<u32, _PERB_DITH5>>

pub fn dithercyb(&mut self) -> DITHERCYB_W<'_>

Bits 0:4 - Dithering Buffer Cycle Number

pub fn perb(&mut self) -> PERB_W<'_>

Bits 5:23 - Period Buffer Value

impl W<u32, Reg<u32, _PERB_DITH6>>

pub fn dithercyb(&mut self) -> DITHERCYB_W<'_>

Bits 0:5 - Dithering Buffer Cycle Number

pub fn perb(&mut self) -> PERB_W<'_>

Bits 6:23 - Period Buffer Value

impl W<u32, Reg<u32, _CCB>>

pub fn ccb(&mut self) -> CCB_W<'_>

Bits 0:23 - Channel Compare/Capture Buffer Value

impl W<u32, Reg<u32, _CCB_DITH4>>

pub fn dithercyb(&mut self) -> DITHERCYB_W<'_>

Bits 0:3 - Dithering Buffer Cycle Number

pub fn ccb(&mut self) -> CCB_W<'_>

Bits 4:23 - Channel Compare/Capture Buffer Value

impl W<u32, Reg<u32, _CCB_DITH5>>

pub fn dithercyb(&mut self) -> DITHERCYB_W<'_>

Bits 0:4 - Dithering Buffer Cycle Number

pub fn ccb(&mut self) -> CCB_W<'_>

Bits 5:23 - Channel Compare/Capture Buffer Value

impl W<u32, Reg<u32, _CCB_DITH6>>

pub fn dithercyb(&mut self) -> DITHERCYB_W<'_>

Bits 0:5 - Dithering Buffer Cycle Number

pub fn ccb(&mut self) -> CCB_W<'_>

Bits 6:23 - Channel Compare/Capture Buffer Value

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 2 - Run in Standby Mode

pub fn mode(&mut self) -> MODE_W<'_>

Bit 7 - Operating Mode

impl W<u8, Reg<u8, _QOSCTRL>>

pub fn cqos(&mut self) -> CQOS_W<'_>

Bits 0:1 - Configuration Quality of Service

pub fn dqos(&mut self) -> DQOS_W<'_>

Bits 2:3 - Data Quality of Service

impl W<u16, Reg<u16, _CTRLB>>

pub fn detach(&mut self) -> DETACH_W<'_>

Bit 0 - Detach

pub fn uprsm(&mut self) -> UPRSM_W<'_>

Bit 1 - Upstream Resume

pub fn spdconf(&mut self) -> SPDCONF_W<'_>

Bits 2:3 - Speed Configuration

pub fn nreply(&mut self) -> NREPLY_W<'_>

Bit 4 - No Reply

pub fn tstj(&mut self) -> TSTJ_W<'_>

Bit 5 - Test mode J

pub fn tstk(&mut self) -> TSTK_W<'_>

Bit 6 - Test mode K

pub fn tstpckt(&mut self) -> TSTPCKT_W<'_>

Bit 7 - Test packet mode

pub fn opmode2(&mut self) -> OPMODE2_W<'_>

Bit 8 - Specific Operational Mode

pub fn gnak(&mut self) -> GNAK_W<'_>

Bit 9 - Global NAK

pub fn lpmhdsk(&mut self) -> LPMHDSK_W<'_>

Bits 10:11 - Link Power Management Handshake

impl W<u8, Reg<u8, _DADD>>

pub fn dadd(&mut self) -> DADD_W<'_>

Bits 0:6 - Device Address

pub fn adden(&mut self) -> ADDEN_W<'_>

Bit 7 - Device Address Enable

impl W<u16, Reg<u16, _INTENCLR>>

pub fn suspend(&mut self) -> SUSPEND_W<'_>

Bit 0 - Suspend Interrupt Enable

pub fn msof(&mut self) -> MSOF_W<'_>

Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode

pub fn sof(&mut self) -> SOF_W<'_>

Bit 2 - Start Of Frame Interrupt Enable

pub fn eorst(&mut self) -> EORST_W<'_>

Bit 3 - End of Reset Interrupt Enable

pub fn wakeup(&mut self) -> WAKEUP_W<'_>

Bit 4 - Wake Up Interrupt Enable

pub fn eorsm(&mut self) -> EORSM_W<'_>

Bit 5 - End Of Resume Interrupt Enable

pub fn uprsm(&mut self) -> UPRSM_W<'_>

Bit 6 - Upstream Resume Interrupt Enable

pub fn ramacer(&mut self) -> RAMACER_W<'_>

Bit 7 - Ram Access Interrupt Enable

pub fn lpmnyet(&mut self) -> LPMNYET_W<'_>

Bit 8 - Link Power Management Not Yet Interrupt Enable

pub fn lpmsusp(&mut self) -> LPMSUSP_W<'_>

Bit 9 - Link Power Management Suspend Interrupt Enable

impl W<u16, Reg<u16, _INTENSET>>

pub fn suspend(&mut self) -> SUSPEND_W<'_>

Bit 0 - Suspend Interrupt Enable

pub fn msof(&mut self) -> MSOF_W<'_>

Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode

pub fn sof(&mut self) -> SOF_W<'_>

Bit 2 - Start Of Frame Interrupt Enable

pub fn eorst(&mut self) -> EORST_W<'_>

Bit 3 - End of Reset Interrupt Enable

pub fn wakeup(&mut self) -> WAKEUP_W<'_>

Bit 4 - Wake Up Interrupt Enable

pub fn eorsm(&mut self) -> EORSM_W<'_>

Bit 5 - End Of Resume Interrupt Enable

pub fn uprsm(&mut self) -> UPRSM_W<'_>

Bit 6 - Upstream Resume Interrupt Enable

pub fn ramacer(&mut self) -> RAMACER_W<'_>

Bit 7 - Ram Access Interrupt Enable

pub fn lpmnyet(&mut self) -> LPMNYET_W<'_>

Bit 8 - Link Power Management Not Yet Interrupt Enable

pub fn lpmsusp(&mut self) -> LPMSUSP_W<'_>

Bit 9 - Link Power Management Suspend Interrupt Enable

impl W<u16, Reg<u16, _INTFLAG>>

pub fn suspend(&mut self) -> SUSPEND_W<'_>

Bit 0 - Suspend

pub fn msof(&mut self) -> MSOF_W<'_>

Bit 1 - Micro Start of Frame in High Speed Mode

pub fn sof(&mut self) -> SOF_W<'_>

Bit 2 - Start Of Frame

pub fn eorst(&mut self) -> EORST_W<'_>

Bit 3 - End of Reset

pub fn wakeup(&mut self) -> WAKEUP_W<'_>

Bit 4 - Wake Up

pub fn eorsm(&mut self) -> EORSM_W<'_>

Bit 5 - End Of Resume

pub fn uprsm(&mut self) -> UPRSM_W<'_>

Bit 6 - Upstream Resume

pub fn ramacer(&mut self) -> RAMACER_W<'_>

Bit 7 - Ram Access

pub fn lpmnyet(&mut self) -> LPMNYET_W<'_>

Bit 8 - Link Power Management Not Yet

pub fn lpmsusp(&mut self) -> LPMSUSP_W<'_>

Bit 9 - Link Power Management Suspend

impl W<u32, Reg<u32, _DESCADD>>

pub fn descadd(&mut self) -> DESCADD_W<'_>

Bits 0:31 - Descriptor Address Value

impl W<u16, Reg<u16, _PADCAL>>

pub fn transp(&mut self) -> TRANSP_W<'_>

Bits 0:4 - USB Pad Transp calibration

pub fn transn(&mut self) -> TRANSN_W<'_>

Bits 6:10 - USB Pad Transn calibration

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 12:14 - USB Pad Trim calibration

impl W<u8, Reg<u8, _EPCFG>>

pub fn eptype0(&mut self) -> EPTYPE0_W<'_>

Bits 0:2 - End Point Type0

pub fn eptype1(&mut self) -> EPTYPE1_W<'_>

Bits 4:6 - End Point Type1

pub fn nyetdis(&mut self) -> NYETDIS_W<'_>

Bit 7 - NYET Token Disable

impl W<u8, Reg<u8, _EPSTATUSCLR>>

pub fn dtglout(&mut self) -> DTGLOUT_W<'_>

Bit 0 - Data Toggle OUT Clear

pub fn dtglin(&mut self) -> DTGLIN_W<'_>

Bit 1 - Data Toggle IN Clear

pub fn curbk(&mut self) -> CURBK_W<'_>

Bit 2 - Current Bank Clear

pub fn stallrq0(&mut self) -> STALLRQ0_W<'_>

Bit 4 - Stall 0 Request Clear

pub fn stallrq1(&mut self) -> STALLRQ1_W<'_>

Bit 5 - Stall 1 Request Clear

pub fn bk0rdy(&mut self) -> BK0RDY_W<'_>

Bit 6 - Bank 0 Ready Clear

pub fn bk1rdy(&mut self) -> BK1RDY_W<'_>

Bit 7 - Bank 1 Ready Clear

impl W<u8, Reg<u8, _EPSTATUSSET>>

pub fn dtglout(&mut self) -> DTGLOUT_W<'_>

Bit 0 - Data Toggle OUT Set

pub fn dtglin(&mut self) -> DTGLIN_W<'_>

Bit 1 - Data Toggle IN Set

pub fn curbk(&mut self) -> CURBK_W<'_>

Bit 2 - Current Bank Set

pub fn stallrq0(&mut self) -> STALLRQ0_W<'_>

Bit 4 - Stall 0 Request Set

pub fn stallrq1(&mut self) -> STALLRQ1_W<'_>

Bit 5 - Stall 1 Request Set

pub fn bk0rdy(&mut self) -> BK0RDY_W<'_>

Bit 6 - Bank 0 Ready Set

pub fn bk1rdy(&mut self) -> BK1RDY_W<'_>

Bit 7 - Bank 1 Ready Set

impl W<u8, Reg<u8, _EPINTFLAG>>

pub fn trcpt0(&mut self) -> TRCPT0_W<'_>

Bit 0 - Transfer Complete 0

pub fn trcpt1(&mut self) -> TRCPT1_W<'_>

Bit 1 - Transfer Complete 1

pub fn trfail0(&mut self) -> TRFAIL0_W<'_>

Bit 2 - Error Flow 0

pub fn trfail1(&mut self) -> TRFAIL1_W<'_>

Bit 3 - Error Flow 1

pub fn rxstp(&mut self) -> RXSTP_W<'_>

Bit 4 - Received Setup

pub fn stall0(&mut self) -> STALL0_W<'_>

Bit 5 - Stall 0 In/out

pub fn stall1(&mut self) -> STALL1_W<'_>

Bit 6 - Stall 1 In/out

impl W<u8, Reg<u8, _EPINTENCLR>>

pub fn trcpt0(&mut self) -> TRCPT0_W<'_>

Bit 0 - Transfer Complete 0 Interrupt Disable

pub fn trcpt1(&mut self) -> TRCPT1_W<'_>

Bit 1 - Transfer Complete 1 Interrupt Disable

pub fn trfail0(&mut self) -> TRFAIL0_W<'_>

Bit 2 - Error Flow 0 Interrupt Disable

pub fn trfail1(&mut self) -> TRFAIL1_W<'_>

Bit 3 - Error Flow 1 Interrupt Disable

pub fn rxstp(&mut self) -> RXSTP_W<'_>

Bit 4 - Received Setup Interrupt Disable

pub fn stall0(&mut self) -> STALL0_W<'_>

Bit 5 - Stall 0 In/Out Interrupt Disable

pub fn stall1(&mut self) -> STALL1_W<'_>

Bit 6 - Stall 1 In/Out Interrupt Disable

impl W<u8, Reg<u8, _EPINTENSET>>

pub fn trcpt0(&mut self) -> TRCPT0_W<'_>

Bit 0 - Transfer Complete 0 Interrupt Enable

pub fn trcpt1(&mut self) -> TRCPT1_W<'_>

Bit 1 - Transfer Complete 1 Interrupt Enable

pub fn trfail0(&mut self) -> TRFAIL0_W<'_>

Bit 2 - Error Flow 0 Interrupt Enable

pub fn trfail1(&mut self) -> TRFAIL1_W<'_>

Bit 3 - Error Flow 1 Interrupt Enable

pub fn rxstp(&mut self) -> RXSTP_W<'_>

Bit 4 - Received Setup Interrupt Enable

pub fn stall0(&mut self) -> STALL0_W<'_>

Bit 5 - Stall 0 In/out Interrupt enable

pub fn stall1(&mut self) -> STALL1_W<'_>

Bit 6 - Stall 1 In/out Interrupt enable

impl W<u8, Reg<u8, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn wen(&mut self) -> WEN_W<'_>

Bit 2 - Watchdog Timer Window Mode Enable

pub fn alwayson(&mut self) -> ALWAYSON_W<'_>

Bit 7 - Always-On

impl W<u8, Reg<u8, _CONFIG>>

pub fn per(&mut self) -> PER_W<'_>

Bits 0:3 - Time-Out Period

pub fn window(&mut self) -> WINDOW_W<'_>

Bits 4:7 - Window Mode Time-Out Period

impl W<u8, Reg<u8, _EWCTRL>>

pub fn ewoffset(&mut self) -> EWOFFSET_W<'_>

Bits 0:3 - Early Warning Interrupt Time Offset

impl W<u8, Reg<u8, _INTENCLR>>

pub fn ew(&mut self) -> EW_W<'_>

Bit 0 - Early Warning Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn ew(&mut self) -> EW_W<'_>

Bit 0 - Early Warning Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn ew(&mut self) -> EW_W<'_>

Bit 0 - Early Warning

impl W<u8, Reg<u8, _CLEAR>>

pub fn clear(&mut self) -> CLEAR_W<'_>

Bits 0:7 - Watchdog Clear