Type Definition atsam4sd32b_pac::udp::csr0_isochronous::W[][src]

type W = W<u32, CSR0_ISOCHRONOUS>;

Writer for register CSR0_ISOCHRONOUS

Implementations

impl W[src]

pub fn txcomp(&mut self) -> TXCOMP_W<'_>[src]

Bit 0 - Generates an IN Packet with Data Previously Written in the DPR

pub fn rx_data_bk0(&mut self) -> RX_DATA_BK0_W<'_>[src]

Bit 1 - Receive Data Bank 0

pub fn rxsetup(&mut self) -> RXSETUP_W<'_>[src]

Bit 2 - Received Setup

pub fn isoerror(&mut self) -> ISOERROR_W<'_>[src]

Bit 3 - A CRC error has been detected in an isochronous transfer

pub fn txpktrdy(&mut self) -> TXPKTRDY_W<'_>[src]

Bit 4 - Transmit Packet Ready

pub fn forcestall(&mut self) -> FORCESTALL_W<'_>[src]

Bit 5 - Force Stall (used by Control, Bulk and Isochronous Endpoints)

pub fn rx_data_bk1(&mut self) -> RX_DATA_BK1_W<'_>[src]

Bit 6 - Receive Data Bank 1 (only used by endpoints with ping-pong attributes)

pub fn dir(&mut self) -> DIR_W<'_>[src]

Bit 7 - Transfer Direction (only available for control endpoints)

pub fn eptype(&mut self) -> EPTYPE_W<'_>[src]

Bits 8:10 - Endpoint Type

pub fn dtgle(&mut self) -> DTGLE_W<'_>[src]

Bit 11 - Data Toggle

pub fn epeds(&mut self) -> EPEDS_W<'_>[src]

Bit 15 - Endpoint Enable Disable

pub fn rxbytecnt(&mut self) -> RXBYTECNT_W<'_>[src]

Bits 16:26 - Number of Bytes Available in the FIFO