Type Definition atsam4sd16b_pac::twi1::sr::R[][src]

type R = R<u32, SR>;

Reader of register SR

Implementations

impl R[src]

pub fn txcomp(&self) -> TXCOMP_R[src]

Bit 0 - Transmission Completed (cleared by writing TWI_THR)

pub fn rxrdy(&self) -> RXRDY_R[src]

Bit 1 - Receive Holding Register Ready (cleared by reading TWI_RHR)

pub fn txrdy(&self) -> TXRDY_R[src]

Bit 2 - Transmit Holding Register Ready (cleared by writing TWI_THR)

pub fn svread(&self) -> SVREAD_R[src]

Bit 3 - Slave Read

pub fn svacc(&self) -> SVACC_R[src]

Bit 4 - Slave Access

pub fn gacc(&self) -> GACC_R[src]

Bit 5 - General Call Access (cleared on read)

pub fn ovre(&self) -> OVRE_R[src]

Bit 6 - Overrun Error (cleared on read)

pub fn nack(&self) -> NACK_R[src]

Bit 8 - Not Acknowledged (cleared on read)

pub fn arblst(&self) -> ARBLST_R[src]

Bit 9 - Arbitration Lost (cleared on read)

pub fn sclws(&self) -> SCLWS_R[src]

Bit 10 - Clock Wait State

pub fn eosacc(&self) -> EOSACC_R[src]

Bit 11 - End Of Slave Access (cleared on read)

pub fn endrx(&self) -> ENDRX_R[src]

Bit 12 - End of RX buffer (cleared by writing TWI_RCR or TWI_RNCR)

pub fn endtx(&self) -> ENDTX_R[src]

Bit 13 - End of TX buffer (cleared by writing TWI_TCR or TWI_TNCR)

pub fn rxbuff(&self) -> RXBUFF_R[src]

Bit 14 - RX Buffer Full (cleared by writing TWI_RCR or TWI_RNCR)

pub fn txbufe(&self) -> TXBUFE_R[src]

Bit 15 - TX Buffer Empty (cleared by writing TWI_TCR or TWI_TNCR)