#[repr(C)]
pub struct RegisterBlock {
Show 101 fields pub clk: Reg<CLK_SPEC>, pub ena: Reg<ENA_SPEC>, pub dis: Reg<DIS_SPEC>, pub sr: Reg<SR_SPEC>, pub ier1: Reg<IER1_SPEC>, pub idr1: Reg<IDR1_SPEC>, pub imr1: Reg<IMR1_SPEC>, pub isr1: Reg<ISR1_SPEC>, pub scm: Reg<SCM_SPEC>, pub scuc: Reg<SCUC_SPEC>, pub scup: Reg<SCUP_SPEC>, pub scupupd: Reg<SCUPUPD_SPEC>, pub ier2: Reg<IER2_SPEC>, pub idr2: Reg<IDR2_SPEC>, pub imr2: Reg<IMR2_SPEC>, pub isr2: Reg<ISR2_SPEC>, pub oov: Reg<OOV_SPEC>, pub os: Reg<OS_SPEC>, pub oss: Reg<OSS_SPEC>, pub osc: Reg<OSC_SPEC>, pub ossupd: Reg<OSSUPD_SPEC>, pub oscupd: Reg<OSCUPD_SPEC>, pub fmr: Reg<FMR_SPEC>, pub fsr: Reg<FSR_SPEC>, pub fcr: Reg<FCR_SPEC>, pub fpv: Reg<FPV_SPEC>, pub fpe: Reg<FPE_SPEC>, pub elmr: [Reg<ELMR_SPEC>; 2], pub smmr: Reg<SMMR_SPEC>, pub wpcr: Reg<WPCR_SPEC>, pub wpsr: Reg<WPSR_SPEC>, pub tpr: Reg<TPR_SPEC>, pub tcr: Reg<TCR_SPEC>, pub tnpr: Reg<TNPR_SPEC>, pub tncr: Reg<TNCR_SPEC>, pub ptcr: Reg<PTCR_SPEC>, pub ptsr: Reg<PTSR_SPEC>, pub cmpv0: Reg<CMPV0_SPEC>, pub cmpvupd0: Reg<CMPVUPD0_SPEC>, pub cmpm0: Reg<CMPM0_SPEC>, pub cmpmupd0: Reg<CMPMUPD0_SPEC>, pub cmpv1: Reg<CMPV1_SPEC>, pub cmpvupd1: Reg<CMPVUPD1_SPEC>, pub cmpm1: Reg<CMPM1_SPEC>, pub cmpmupd1: Reg<CMPMUPD1_SPEC>, pub cmpv2: Reg<CMPV2_SPEC>, pub cmpvupd2: Reg<CMPVUPD2_SPEC>, pub cmpm2: Reg<CMPM2_SPEC>, pub cmpmupd2: Reg<CMPMUPD2_SPEC>, pub cmpv3: Reg<CMPV3_SPEC>, pub cmpvupd3: Reg<CMPVUPD3_SPEC>, pub cmpm3: Reg<CMPM3_SPEC>, pub cmpmupd3: Reg<CMPMUPD3_SPEC>, pub cmpv4: Reg<CMPV4_SPEC>, pub cmpvupd4: Reg<CMPVUPD4_SPEC>, pub cmpm4: Reg<CMPM4_SPEC>, pub cmpmupd4: Reg<CMPMUPD4_SPEC>, pub cmpv5: Reg<CMPV5_SPEC>, pub cmpvupd5: Reg<CMPVUPD5_SPEC>, pub cmpm5: Reg<CMPM5_SPEC>, pub cmpmupd5: Reg<CMPMUPD5_SPEC>, pub cmpv6: Reg<CMPV6_SPEC>, pub cmpvupd6: Reg<CMPVUPD6_SPEC>, pub cmpm6: Reg<CMPM6_SPEC>, pub cmpmupd6: Reg<CMPMUPD6_SPEC>, pub cmpv7: Reg<CMPV7_SPEC>, pub cmpvupd7: Reg<CMPVUPD7_SPEC>, pub cmpm7: Reg<CMPM7_SPEC>, pub cmpmupd7: Reg<CMPMUPD7_SPEC>, pub cmr0: Reg<CMR0_SPEC>, pub cdty0: Reg<CDTY0_SPEC>, pub cdtyupd0: Reg<CDTYUPD0_SPEC>, pub cprd0: Reg<CPRD0_SPEC>, pub cprdupd0: Reg<CPRDUPD0_SPEC>, pub ccnt0: Reg<CCNT0_SPEC>, pub dt0: Reg<DT0_SPEC>, pub dtupd0: Reg<DTUPD0_SPEC>, pub cmr1: Reg<CMR1_SPEC>, pub cdty1: Reg<CDTY1_SPEC>, pub cdtyupd1: Reg<CDTYUPD1_SPEC>, pub cprd1: Reg<CPRD1_SPEC>, pub cprdupd1: Reg<CPRDUPD1_SPEC>, pub ccnt1: Reg<CCNT1_SPEC>, pub dt1: Reg<DT1_SPEC>, pub dtupd1: Reg<DTUPD1_SPEC>, pub cmr2: Reg<CMR2_SPEC>, pub cdty2: Reg<CDTY2_SPEC>, pub cdtyupd2: Reg<CDTYUPD2_SPEC>, pub cprd2: Reg<CPRD2_SPEC>, pub cprdupd2: Reg<CPRDUPD2_SPEC>, pub ccnt2: Reg<CCNT2_SPEC>, pub dt2: Reg<DT2_SPEC>, pub dtupd2: Reg<DTUPD2_SPEC>, pub cmr3: Reg<CMR3_SPEC>, pub cdty3: Reg<CDTY3_SPEC>, pub cdtyupd3: Reg<CDTYUPD3_SPEC>, pub cprd3: Reg<CPRD3_SPEC>, pub cprdupd3: Reg<CPRDUPD3_SPEC>, pub ccnt3: Reg<CCNT3_SPEC>, pub dt3: Reg<DT3_SPEC>, pub dtupd3: Reg<DTUPD3_SPEC>, /* private fields */
}
Expand description

Register block

Fields

clk: Reg<CLK_SPEC>

0x00 - PWM Clock Register

ena: Reg<ENA_SPEC>

0x04 - PWM Enable Register

dis: Reg<DIS_SPEC>

0x08 - PWM Disable Register

sr: Reg<SR_SPEC>

0x0c - PWM Status Register

ier1: Reg<IER1_SPEC>

0x10 - PWM Interrupt Enable Register 1

idr1: Reg<IDR1_SPEC>

0x14 - PWM Interrupt Disable Register 1

imr1: Reg<IMR1_SPEC>

0x18 - PWM Interrupt Mask Register 1

isr1: Reg<ISR1_SPEC>

0x1c - PWM Interrupt Status Register 1

scm: Reg<SCM_SPEC>

0x20 - PWM Sync Channels Mode Register

scuc: Reg<SCUC_SPEC>

0x28 - PWM Sync Channels Update Control Register

scup: Reg<SCUP_SPEC>

0x2c - PWM Sync Channels Update Period Register

scupupd: Reg<SCUPUPD_SPEC>

0x30 - PWM Sync Channels Update Period Update Register

ier2: Reg<IER2_SPEC>

0x34 - PWM Interrupt Enable Register 2

idr2: Reg<IDR2_SPEC>

0x38 - PWM Interrupt Disable Register 2

imr2: Reg<IMR2_SPEC>

0x3c - PWM Interrupt Mask Register 2

isr2: Reg<ISR2_SPEC>

0x40 - PWM Interrupt Status Register 2

oov: Reg<OOV_SPEC>

0x44 - PWM Output Override Value Register

os: Reg<OS_SPEC>

0x48 - PWM Output Selection Register

oss: Reg<OSS_SPEC>

0x4c - PWM Output Selection Set Register

osc: Reg<OSC_SPEC>

0x50 - PWM Output Selection Clear Register

ossupd: Reg<OSSUPD_SPEC>

0x54 - PWM Output Selection Set Update Register

oscupd: Reg<OSCUPD_SPEC>

0x58 - PWM Output Selection Clear Update Register

fmr: Reg<FMR_SPEC>

0x5c - PWM Fault Mode Register

fsr: Reg<FSR_SPEC>

0x60 - PWM Fault Status Register

fcr: Reg<FCR_SPEC>

0x64 - PWM Fault Clear Register

fpv: Reg<FPV_SPEC>

0x68 - PWM Fault Protection Value Register

fpe: Reg<FPE_SPEC>

0x6c - PWM Fault Protection Enable Register

elmr: [Reg<ELMR_SPEC>; 2]

0x7c..0x84 - PWM Event Line 0 Mode Register

smmr: Reg<SMMR_SPEC>

0xb0 - PWM Stepper Motor Mode Register

wpcr: Reg<WPCR_SPEC>

0xe4 - PWM Write Protection Control Register

wpsr: Reg<WPSR_SPEC>

0xe8 - PWM Write Protection Status Register

tpr: Reg<TPR_SPEC>

0x108 - Transmit Pointer Register

tcr: Reg<TCR_SPEC>

0x10c - Transmit Counter Register

tnpr: Reg<TNPR_SPEC>

0x118 - Transmit Next Pointer Register

tncr: Reg<TNCR_SPEC>

0x11c - Transmit Next Counter Register

ptcr: Reg<PTCR_SPEC>

0x120 - Transfer Control Register

ptsr: Reg<PTSR_SPEC>

0x124 - Transfer Status Register

cmpv0: Reg<CMPV0_SPEC>

0x130 - PWM Comparison 0 Value Register

cmpvupd0: Reg<CMPVUPD0_SPEC>

0x134 - PWM Comparison 0 Value Update Register

cmpm0: Reg<CMPM0_SPEC>

0x138 - PWM Comparison 0 Mode Register

cmpmupd0: Reg<CMPMUPD0_SPEC>

0x13c - PWM Comparison 0 Mode Update Register

cmpv1: Reg<CMPV1_SPEC>

0x140 - PWM Comparison 1 Value Register

cmpvupd1: Reg<CMPVUPD1_SPEC>

0x144 - PWM Comparison 1 Value Update Register

cmpm1: Reg<CMPM1_SPEC>

0x148 - PWM Comparison 1 Mode Register

cmpmupd1: Reg<CMPMUPD1_SPEC>

0x14c - PWM Comparison 1 Mode Update Register

cmpv2: Reg<CMPV2_SPEC>

0x150 - PWM Comparison 2 Value Register

cmpvupd2: Reg<CMPVUPD2_SPEC>

0x154 - PWM Comparison 2 Value Update Register

cmpm2: Reg<CMPM2_SPEC>

0x158 - PWM Comparison 2 Mode Register

cmpmupd2: Reg<CMPMUPD2_SPEC>

0x15c - PWM Comparison 2 Mode Update Register

cmpv3: Reg<CMPV3_SPEC>

0x160 - PWM Comparison 3 Value Register

cmpvupd3: Reg<CMPVUPD3_SPEC>

0x164 - PWM Comparison 3 Value Update Register

cmpm3: Reg<CMPM3_SPEC>

0x168 - PWM Comparison 3 Mode Register

cmpmupd3: Reg<CMPMUPD3_SPEC>

0x16c - PWM Comparison 3 Mode Update Register

cmpv4: Reg<CMPV4_SPEC>

0x170 - PWM Comparison 4 Value Register

cmpvupd4: Reg<CMPVUPD4_SPEC>

0x174 - PWM Comparison 4 Value Update Register

cmpm4: Reg<CMPM4_SPEC>

0x178 - PWM Comparison 4 Mode Register

cmpmupd4: Reg<CMPMUPD4_SPEC>

0x17c - PWM Comparison 4 Mode Update Register

cmpv5: Reg<CMPV5_SPEC>

0x180 - PWM Comparison 5 Value Register

cmpvupd5: Reg<CMPVUPD5_SPEC>

0x184 - PWM Comparison 5 Value Update Register

cmpm5: Reg<CMPM5_SPEC>

0x188 - PWM Comparison 5 Mode Register

cmpmupd5: Reg<CMPMUPD5_SPEC>

0x18c - PWM Comparison 5 Mode Update Register

cmpv6: Reg<CMPV6_SPEC>

0x190 - PWM Comparison 6 Value Register

cmpvupd6: Reg<CMPVUPD6_SPEC>

0x194 - PWM Comparison 6 Value Update Register

cmpm6: Reg<CMPM6_SPEC>

0x198 - PWM Comparison 6 Mode Register

cmpmupd6: Reg<CMPMUPD6_SPEC>

0x19c - PWM Comparison 6 Mode Update Register

cmpv7: Reg<CMPV7_SPEC>

0x1a0 - PWM Comparison 7 Value Register

cmpvupd7: Reg<CMPVUPD7_SPEC>

0x1a4 - PWM Comparison 7 Value Update Register

cmpm7: Reg<CMPM7_SPEC>

0x1a8 - PWM Comparison 7 Mode Register

cmpmupd7: Reg<CMPMUPD7_SPEC>

0x1ac - PWM Comparison 7 Mode Update Register

cmr0: Reg<CMR0_SPEC>

0x200 - PWM Channel Mode Register (ch_num = 0)

cdty0: Reg<CDTY0_SPEC>

0x204 - PWM Channel Duty Cycle Register (ch_num = 0)

cdtyupd0: Reg<CDTYUPD0_SPEC>

0x208 - PWM Channel Duty Cycle Update Register (ch_num = 0)

cprd0: Reg<CPRD0_SPEC>

0x20c - PWM Channel Period Register (ch_num = 0)

cprdupd0: Reg<CPRDUPD0_SPEC>

0x210 - PWM Channel Period Update Register (ch_num = 0)

ccnt0: Reg<CCNT0_SPEC>

0x214 - PWM Channel Counter Register (ch_num = 0)

dt0: Reg<DT0_SPEC>

0x218 - PWM Channel Dead Time Register (ch_num = 0)

dtupd0: Reg<DTUPD0_SPEC>

0x21c - PWM Channel Dead Time Update Register (ch_num = 0)

cmr1: Reg<CMR1_SPEC>

0x220 - PWM Channel Mode Register (ch_num = 1)

cdty1: Reg<CDTY1_SPEC>

0x224 - PWM Channel Duty Cycle Register (ch_num = 1)

cdtyupd1: Reg<CDTYUPD1_SPEC>

0x228 - PWM Channel Duty Cycle Update Register (ch_num = 1)

cprd1: Reg<CPRD1_SPEC>

0x22c - PWM Channel Period Register (ch_num = 1)

cprdupd1: Reg<CPRDUPD1_SPEC>

0x230 - PWM Channel Period Update Register (ch_num = 1)

ccnt1: Reg<CCNT1_SPEC>

0x234 - PWM Channel Counter Register (ch_num = 1)

dt1: Reg<DT1_SPEC>

0x238 - PWM Channel Dead Time Register (ch_num = 1)

dtupd1: Reg<DTUPD1_SPEC>

0x23c - PWM Channel Dead Time Update Register (ch_num = 1)

cmr2: Reg<CMR2_SPEC>

0x240 - PWM Channel Mode Register (ch_num = 2)

cdty2: Reg<CDTY2_SPEC>

0x244 - PWM Channel Duty Cycle Register (ch_num = 2)

cdtyupd2: Reg<CDTYUPD2_SPEC>

0x248 - PWM Channel Duty Cycle Update Register (ch_num = 2)

cprd2: Reg<CPRD2_SPEC>

0x24c - PWM Channel Period Register (ch_num = 2)

cprdupd2: Reg<CPRDUPD2_SPEC>

0x250 - PWM Channel Period Update Register (ch_num = 2)

ccnt2: Reg<CCNT2_SPEC>

0x254 - PWM Channel Counter Register (ch_num = 2)

dt2: Reg<DT2_SPEC>

0x258 - PWM Channel Dead Time Register (ch_num = 2)

dtupd2: Reg<DTUPD2_SPEC>

0x25c - PWM Channel Dead Time Update Register (ch_num = 2)

cmr3: Reg<CMR3_SPEC>

0x260 - PWM Channel Mode Register (ch_num = 3)

cdty3: Reg<CDTY3_SPEC>

0x264 - PWM Channel Duty Cycle Register (ch_num = 3)

cdtyupd3: Reg<CDTYUPD3_SPEC>

0x268 - PWM Channel Duty Cycle Update Register (ch_num = 3)

cprd3: Reg<CPRD3_SPEC>

0x26c - PWM Channel Period Register (ch_num = 3)

cprdupd3: Reg<CPRDUPD3_SPEC>

0x270 - PWM Channel Period Update Register (ch_num = 3)

ccnt3: Reg<CCNT3_SPEC>

0x274 - PWM Channel Counter Register (ch_num = 3)

dt3: Reg<DT3_SPEC>

0x278 - PWM Channel Dead Time Register (ch_num = 3)

dtupd3: Reg<DTUPD3_SPEC>

0x27c - PWM Channel Dead Time Update Register (ch_num = 3)

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