Struct atsam4s8c_pac::matrix::RegisterBlock[−][src]

#[repr(C)]pub struct RegisterBlock {
    pub matrix_mcfg: [Reg<MATRIX_MCFG_SPEC>; 4],
    pub matrix_scfg: [Reg<MATRIX_SCFG_SPEC>; 5],
    pub matrix_pras0: Reg<MATRIX_PRAS0_SPEC>,
    pub matrix_pras1: Reg<MATRIX_PRAS1_SPEC>,
    pub matrix_pras2: Reg<MATRIX_PRAS2_SPEC>,
    pub matrix_pras3: Reg<MATRIX_PRAS3_SPEC>,
    pub matrix_pras4: Reg<MATRIX_PRAS4_SPEC>,
    pub ccfg_sysio: Reg<CCFG_SYSIO_SPEC>,
    pub ccfg_smcnfcs: Reg<CCFG_SMCNFCS_SPEC>,
    pub matrix_wpmr: Reg<MATRIX_WPMR_SPEC>,
    pub matrix_wpsr: Reg<MATRIX_WPSR_SPEC>,
    // some fields omitted
}

Expand description

Register block

Fields

matrix_mcfg: [Reg<MATRIX_MCFG_SPEC>; 4]

0x00..0x10 - Master Configuration Register

matrix_scfg: [Reg<MATRIX_SCFG_SPEC>; 5]

0x40..0x54 - Slave Configuration Register

matrix_pras0: Reg<MATRIX_PRAS0_SPEC>

0x80 - Priority Register A for Slave 0

matrix_pras1: Reg<MATRIX_PRAS1_SPEC>

0x88 - Priority Register A for Slave 1

matrix_pras2: Reg<MATRIX_PRAS2_SPEC>

0x90 - Priority Register A for Slave 2

matrix_pras3: Reg<MATRIX_PRAS3_SPEC>

0x98 - Priority Register A for Slave 3

matrix_pras4: Reg<MATRIX_PRAS4_SPEC>

0xa0 - Priority Register A for Slave 4

ccfg_sysio: Reg<CCFG_SYSIO_SPEC>

0x114 - System I/O Configuration register

ccfg_smcnfcs: Reg<CCFG_SMCNFCS_SPEC>

0x11c - SMC Chip Select NAND Flash Assignment Register

matrix_wpmr: Reg<MATRIX_WPMR_SPEC>

0x1e4 - Write Protection Mode Register

matrix_wpsr: Reg<MATRIX_WPSR_SPEC>

0x1e8 - Write Protection Status Register

Auto Trait Implementations

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations

impl<T> Any for T where
T: 'static + ?Sized,

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Performs the conversion.