Struct atsam4lc8b_pac::pdca::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 206 fields
pub mar0: Reg<MAR_SPEC>,
pub psr0: Reg<PSR_SPEC>,
pub tcr0: Reg<TCR_SPEC>,
pub marr0: Reg<MARR_SPEC>,
pub tcrr0: Reg<TCRR_SPEC>,
pub cr0: Reg<CR_SPEC>,
pub mr0: Reg<MR_SPEC>,
pub sr0: Reg<SR_SPEC>,
pub ier0: Reg<IER_SPEC>,
pub idr0: Reg<IDR_SPEC>,
pub imr0: Reg<IMR_SPEC>,
pub isr0: Reg<ISR_SPEC>,
pub mar1: Reg<MAR_SPEC>,
pub psr1: Reg<PSR_SPEC>,
pub tcr1: Reg<TCR_SPEC>,
pub marr1: Reg<MARR_SPEC>,
pub tcrr1: Reg<TCRR_SPEC>,
pub cr1: Reg<CR_SPEC>,
pub mr1: Reg<MR_SPEC>,
pub sr1: Reg<SR_SPEC>,
pub ier1: Reg<IER_SPEC>,
pub idr1: Reg<IDR_SPEC>,
pub imr1: Reg<IMR_SPEC>,
pub isr1: Reg<ISR_SPEC>,
pub mar2: Reg<MAR_SPEC>,
pub psr2: Reg<PSR_SPEC>,
pub tcr2: Reg<TCR_SPEC>,
pub marr2: Reg<MARR_SPEC>,
pub tcrr2: Reg<TCRR_SPEC>,
pub cr2: Reg<CR_SPEC>,
pub mr2: Reg<MR_SPEC>,
pub sr2: Reg<SR_SPEC>,
pub ier2: Reg<IER_SPEC>,
pub idr2: Reg<IDR_SPEC>,
pub imr2: Reg<IMR_SPEC>,
pub isr2: Reg<ISR_SPEC>,
pub mar3: Reg<MAR_SPEC>,
pub psr3: Reg<PSR_SPEC>,
pub tcr3: Reg<TCR_SPEC>,
pub marr3: Reg<MARR_SPEC>,
pub tcrr3: Reg<TCRR_SPEC>,
pub cr3: Reg<CR_SPEC>,
pub mr3: Reg<MR_SPEC>,
pub sr3: Reg<SR_SPEC>,
pub ier3: Reg<IER_SPEC>,
pub idr3: Reg<IDR_SPEC>,
pub imr3: Reg<IMR_SPEC>,
pub isr3: Reg<ISR_SPEC>,
pub mar4: Reg<MAR_SPEC>,
pub psr4: Reg<PSR_SPEC>,
pub tcr4: Reg<TCR_SPEC>,
pub marr4: Reg<MARR_SPEC>,
pub tcrr4: Reg<TCRR_SPEC>,
pub cr4: Reg<CR_SPEC>,
pub mr4: Reg<MR_SPEC>,
pub sr4: Reg<SR_SPEC>,
pub ier4: Reg<IER_SPEC>,
pub idr4: Reg<IDR_SPEC>,
pub imr4: Reg<IMR_SPEC>,
pub isr4: Reg<ISR_SPEC>,
pub mar5: Reg<MAR_SPEC>,
pub psr5: Reg<PSR_SPEC>,
pub tcr5: Reg<TCR_SPEC>,
pub marr5: Reg<MARR_SPEC>,
pub tcrr5: Reg<TCRR_SPEC>,
pub cr5: Reg<CR_SPEC>,
pub mr5: Reg<MR_SPEC>,
pub sr5: Reg<SR_SPEC>,
pub ier5: Reg<IER_SPEC>,
pub idr5: Reg<IDR_SPEC>,
pub imr5: Reg<IMR_SPEC>,
pub isr5: Reg<ISR_SPEC>,
pub mar6: Reg<MAR_SPEC>,
pub psr6: Reg<PSR_SPEC>,
pub tcr6: Reg<TCR_SPEC>,
pub marr6: Reg<MARR_SPEC>,
pub tcrr6: Reg<TCRR_SPEC>,
pub cr6: Reg<CR_SPEC>,
pub mr6: Reg<MR_SPEC>,
pub sr6: Reg<SR_SPEC>,
pub ier6: Reg<IER_SPEC>,
pub idr6: Reg<IDR_SPEC>,
pub imr6: Reg<IMR_SPEC>,
pub isr6: Reg<ISR_SPEC>,
pub mar7: Reg<MAR_SPEC>,
pub psr7: Reg<PSR_SPEC>,
pub tcr7: Reg<TCR_SPEC>,
pub marr7: Reg<MARR_SPEC>,
pub tcrr7: Reg<TCRR_SPEC>,
pub cr7: Reg<CR_SPEC>,
pub mr7: Reg<MR_SPEC>,
pub sr7: Reg<SR_SPEC>,
pub ier7: Reg<IER_SPEC>,
pub idr7: Reg<IDR_SPEC>,
pub imr7: Reg<IMR_SPEC>,
pub isr7: Reg<ISR_SPEC>,
pub mar8: Reg<MAR_SPEC>,
pub psr8: Reg<PSR_SPEC>,
pub tcr8: Reg<TCR_SPEC>,
pub marr8: Reg<MARR_SPEC>,
pub tcrr8: Reg<TCRR_SPEC>,
pub cr8: Reg<CR_SPEC>,
pub mr8: Reg<MR_SPEC>,
pub sr8: Reg<SR_SPEC>,
pub ier8: Reg<IER_SPEC>,
pub idr8: Reg<IDR_SPEC>,
pub imr8: Reg<IMR_SPEC>,
pub isr8: Reg<ISR_SPEC>,
pub mar9: Reg<MAR_SPEC>,
pub psr9: Reg<PSR_SPEC>,
pub tcr9: Reg<TCR_SPEC>,
pub marr9: Reg<MARR_SPEC>,
pub tcrr9: Reg<TCRR_SPEC>,
pub cr9: Reg<CR_SPEC>,
pub mr9: Reg<MR_SPEC>,
pub sr9: Reg<SR_SPEC>,
pub ier9: Reg<IER_SPEC>,
pub idr9: Reg<IDR_SPEC>,
pub imr9: Reg<IMR_SPEC>,
pub isr9: Reg<ISR_SPEC>,
pub mar10: Reg<MAR_SPEC>,
pub psr10: Reg<PSR_SPEC>,
pub tcr10: Reg<TCR_SPEC>,
pub marr10: Reg<MARR_SPEC>,
pub tcrr10: Reg<TCRR_SPEC>,
pub cr10: Reg<CR_SPEC>,
pub mr10: Reg<MR_SPEC>,
pub sr10: Reg<SR_SPEC>,
pub ier10: Reg<IER_SPEC>,
pub idr10: Reg<IDR_SPEC>,
pub imr10: Reg<IMR_SPEC>,
pub isr10: Reg<ISR_SPEC>,
pub mar11: Reg<MAR_SPEC>,
pub psr11: Reg<PSR_SPEC>,
pub tcr11: Reg<TCR_SPEC>,
pub marr11: Reg<MARR_SPEC>,
pub tcrr11: Reg<TCRR_SPEC>,
pub cr11: Reg<CR_SPEC>,
pub mr11: Reg<MR_SPEC>,
pub sr11: Reg<SR_SPEC>,
pub ier11: Reg<IER_SPEC>,
pub idr11: Reg<IDR_SPEC>,
pub imr11: Reg<IMR_SPEC>,
pub isr11: Reg<ISR_SPEC>,
pub mar12: Reg<MAR_SPEC>,
pub psr12: Reg<PSR_SPEC>,
pub tcr12: Reg<TCR_SPEC>,
pub marr12: Reg<MARR_SPEC>,
pub tcrr12: Reg<TCRR_SPEC>,
pub cr12: Reg<CR_SPEC>,
pub mr12: Reg<MR_SPEC>,
pub sr12: Reg<SR_SPEC>,
pub ier12: Reg<IER_SPEC>,
pub idr12: Reg<IDR_SPEC>,
pub imr12: Reg<IMR_SPEC>,
pub isr12: Reg<ISR_SPEC>,
pub mar13: Reg<MAR_SPEC>,
pub psr13: Reg<PSR_SPEC>,
pub tcr13: Reg<TCR_SPEC>,
pub marr13: Reg<MARR_SPEC>,
pub tcrr13: Reg<TCRR_SPEC>,
pub cr13: Reg<CR_SPEC>,
pub mr13: Reg<MR_SPEC>,
pub sr13: Reg<SR_SPEC>,
pub ier13: Reg<IER_SPEC>,
pub idr13: Reg<IDR_SPEC>,
pub imr13: Reg<IMR_SPEC>,
pub isr13: Reg<ISR_SPEC>,
pub mar14: Reg<MAR_SPEC>,
pub psr14: Reg<PSR_SPEC>,
pub tcr14: Reg<TCR_SPEC>,
pub marr14: Reg<MARR_SPEC>,
pub tcrr14: Reg<TCRR_SPEC>,
pub cr14: Reg<CR_SPEC>,
pub mr14: Reg<MR_SPEC>,
pub sr14: Reg<SR_SPEC>,
pub ier14: Reg<IER_SPEC>,
pub idr14: Reg<IDR_SPEC>,
pub imr14: Reg<IMR_SPEC>,
pub isr14: Reg<ISR_SPEC>,
pub mar15: Reg<MAR_SPEC>,
pub psr15: Reg<PSR_SPEC>,
pub tcr15: Reg<TCR_SPEC>,
pub marr15: Reg<MARR_SPEC>,
pub tcrr15: Reg<TCRR_SPEC>,
pub cr15: Reg<CR_SPEC>,
pub mr15: Reg<MR_SPEC>,
pub sr15: Reg<SR_SPEC>,
pub ier15: Reg<IER_SPEC>,
pub idr15: Reg<IDR_SPEC>,
pub imr15: Reg<IMR_SPEC>,
pub isr15: Reg<ISR_SPEC>,
pub pcontrol: Reg<PCONTROL_SPEC>,
pub prdata0: Reg<PRDATA0_SPEC>,
pub prstall0: Reg<PRSTALL0_SPEC>,
pub prlat0: Reg<PRLAT0_SPEC>,
pub pwdata0: Reg<PWDATA0_SPEC>,
pub pwstall0: Reg<PWSTALL0_SPEC>,
pub pwlat0: Reg<PWLAT0_SPEC>,
pub prdata1: Reg<PRDATA1_SPEC>,
pub prstall1: Reg<PRSTALL1_SPEC>,
pub prlat1: Reg<PRLAT1_SPEC>,
pub pwdata1: Reg<PWDATA1_SPEC>,
pub pwstall1: Reg<PWSTALL1_SPEC>,
pub pwlat1: Reg<PWLAT1_SPEC>,
pub version: Reg<VERSION_SPEC>,
// some fields omitted
}Expand description
Register block
Fields
mar0: Reg<MAR_SPEC>0x00 - Memory Address Register
psr0: Reg<PSR_SPEC>0x04 - Peripheral Select Register
tcr0: Reg<TCR_SPEC>0x08 - Transfer Counter Register
marr0: Reg<MARR_SPEC>0x0c - Memory Address Reload Register
tcrr0: Reg<TCRR_SPEC>0x10 - Transfer Counter Reload Register
cr0: Reg<CR_SPEC>0x14 - Control Register
mr0: Reg<MR_SPEC>0x18 - Mode Register
sr0: Reg<SR_SPEC>0x1c - Status Register
ier0: Reg<IER_SPEC>0x20 - Interrupt Enable Register
idr0: Reg<IDR_SPEC>0x24 - Interrupt Disable Register
imr0: Reg<IMR_SPEC>0x28 - Interrupt Mask Register
isr0: Reg<ISR_SPEC>0x2c - Interrupt Status Register
mar1: Reg<MAR_SPEC>0x40 - Memory Address Register
psr1: Reg<PSR_SPEC>0x44 - Peripheral Select Register
tcr1: Reg<TCR_SPEC>0x48 - Transfer Counter Register
marr1: Reg<MARR_SPEC>0x4c - Memory Address Reload Register
tcrr1: Reg<TCRR_SPEC>0x50 - Transfer Counter Reload Register
cr1: Reg<CR_SPEC>0x54 - Control Register
mr1: Reg<MR_SPEC>0x58 - Mode Register
sr1: Reg<SR_SPEC>0x5c - Status Register
ier1: Reg<IER_SPEC>0x60 - Interrupt Enable Register
idr1: Reg<IDR_SPEC>0x64 - Interrupt Disable Register
imr1: Reg<IMR_SPEC>0x68 - Interrupt Mask Register
isr1: Reg<ISR_SPEC>0x6c - Interrupt Status Register
mar2: Reg<MAR_SPEC>0x80 - Memory Address Register
psr2: Reg<PSR_SPEC>0x84 - Peripheral Select Register
tcr2: Reg<TCR_SPEC>0x88 - Transfer Counter Register
marr2: Reg<MARR_SPEC>0x8c - Memory Address Reload Register
tcrr2: Reg<TCRR_SPEC>0x90 - Transfer Counter Reload Register
cr2: Reg<CR_SPEC>0x94 - Control Register
mr2: Reg<MR_SPEC>0x98 - Mode Register
sr2: Reg<SR_SPEC>0x9c - Status Register
ier2: Reg<IER_SPEC>0xa0 - Interrupt Enable Register
idr2: Reg<IDR_SPEC>0xa4 - Interrupt Disable Register
imr2: Reg<IMR_SPEC>0xa8 - Interrupt Mask Register
isr2: Reg<ISR_SPEC>0xac - Interrupt Status Register
mar3: Reg<MAR_SPEC>0xc0 - Memory Address Register
psr3: Reg<PSR_SPEC>0xc4 - Peripheral Select Register
tcr3: Reg<TCR_SPEC>0xc8 - Transfer Counter Register
marr3: Reg<MARR_SPEC>0xcc - Memory Address Reload Register
tcrr3: Reg<TCRR_SPEC>0xd0 - Transfer Counter Reload Register
cr3: Reg<CR_SPEC>0xd4 - Control Register
mr3: Reg<MR_SPEC>0xd8 - Mode Register
sr3: Reg<SR_SPEC>0xdc - Status Register
ier3: Reg<IER_SPEC>0xe0 - Interrupt Enable Register
idr3: Reg<IDR_SPEC>0xe4 - Interrupt Disable Register
imr3: Reg<IMR_SPEC>0xe8 - Interrupt Mask Register
isr3: Reg<ISR_SPEC>0xec - Interrupt Status Register
mar4: Reg<MAR_SPEC>0x100 - Memory Address Register
psr4: Reg<PSR_SPEC>0x104 - Peripheral Select Register
tcr4: Reg<TCR_SPEC>0x108 - Transfer Counter Register
marr4: Reg<MARR_SPEC>0x10c - Memory Address Reload Register
tcrr4: Reg<TCRR_SPEC>0x110 - Transfer Counter Reload Register
cr4: Reg<CR_SPEC>0x114 - Control Register
mr4: Reg<MR_SPEC>0x118 - Mode Register
sr4: Reg<SR_SPEC>0x11c - Status Register
ier4: Reg<IER_SPEC>0x120 - Interrupt Enable Register
idr4: Reg<IDR_SPEC>0x124 - Interrupt Disable Register
imr4: Reg<IMR_SPEC>0x128 - Interrupt Mask Register
isr4: Reg<ISR_SPEC>0x12c - Interrupt Status Register
mar5: Reg<MAR_SPEC>0x140 - Memory Address Register
psr5: Reg<PSR_SPEC>0x144 - Peripheral Select Register
tcr5: Reg<TCR_SPEC>0x148 - Transfer Counter Register
marr5: Reg<MARR_SPEC>0x14c - Memory Address Reload Register
tcrr5: Reg<TCRR_SPEC>0x150 - Transfer Counter Reload Register
cr5: Reg<CR_SPEC>0x154 - Control Register
mr5: Reg<MR_SPEC>0x158 - Mode Register
sr5: Reg<SR_SPEC>0x15c - Status Register
ier5: Reg<IER_SPEC>0x160 - Interrupt Enable Register
idr5: Reg<IDR_SPEC>0x164 - Interrupt Disable Register
imr5: Reg<IMR_SPEC>0x168 - Interrupt Mask Register
isr5: Reg<ISR_SPEC>0x16c - Interrupt Status Register
mar6: Reg<MAR_SPEC>0x180 - Memory Address Register
psr6: Reg<PSR_SPEC>0x184 - Peripheral Select Register
tcr6: Reg<TCR_SPEC>0x188 - Transfer Counter Register
marr6: Reg<MARR_SPEC>0x18c - Memory Address Reload Register
tcrr6: Reg<TCRR_SPEC>0x190 - Transfer Counter Reload Register
cr6: Reg<CR_SPEC>0x194 - Control Register
mr6: Reg<MR_SPEC>0x198 - Mode Register
sr6: Reg<SR_SPEC>0x19c - Status Register
ier6: Reg<IER_SPEC>0x1a0 - Interrupt Enable Register
idr6: Reg<IDR_SPEC>0x1a4 - Interrupt Disable Register
imr6: Reg<IMR_SPEC>0x1a8 - Interrupt Mask Register
isr6: Reg<ISR_SPEC>0x1ac - Interrupt Status Register
mar7: Reg<MAR_SPEC>0x1c0 - Memory Address Register
psr7: Reg<PSR_SPEC>0x1c4 - Peripheral Select Register
tcr7: Reg<TCR_SPEC>0x1c8 - Transfer Counter Register
marr7: Reg<MARR_SPEC>0x1cc - Memory Address Reload Register
tcrr7: Reg<TCRR_SPEC>0x1d0 - Transfer Counter Reload Register
cr7: Reg<CR_SPEC>0x1d4 - Control Register
mr7: Reg<MR_SPEC>0x1d8 - Mode Register
sr7: Reg<SR_SPEC>0x1dc - Status Register
ier7: Reg<IER_SPEC>0x1e0 - Interrupt Enable Register
idr7: Reg<IDR_SPEC>0x1e4 - Interrupt Disable Register
imr7: Reg<IMR_SPEC>0x1e8 - Interrupt Mask Register
isr7: Reg<ISR_SPEC>0x1ec - Interrupt Status Register
mar8: Reg<MAR_SPEC>0x200 - Memory Address Register
psr8: Reg<PSR_SPEC>0x204 - Peripheral Select Register
tcr8: Reg<TCR_SPEC>0x208 - Transfer Counter Register
marr8: Reg<MARR_SPEC>0x20c - Memory Address Reload Register
tcrr8: Reg<TCRR_SPEC>0x210 - Transfer Counter Reload Register
cr8: Reg<CR_SPEC>0x214 - Control Register
mr8: Reg<MR_SPEC>0x218 - Mode Register
sr8: Reg<SR_SPEC>0x21c - Status Register
ier8: Reg<IER_SPEC>0x220 - Interrupt Enable Register
idr8: Reg<IDR_SPEC>0x224 - Interrupt Disable Register
imr8: Reg<IMR_SPEC>0x228 - Interrupt Mask Register
isr8: Reg<ISR_SPEC>0x22c - Interrupt Status Register
mar9: Reg<MAR_SPEC>0x240 - Memory Address Register
psr9: Reg<PSR_SPEC>0x244 - Peripheral Select Register
tcr9: Reg<TCR_SPEC>0x248 - Transfer Counter Register
marr9: Reg<MARR_SPEC>0x24c - Memory Address Reload Register
tcrr9: Reg<TCRR_SPEC>0x250 - Transfer Counter Reload Register
cr9: Reg<CR_SPEC>0x254 - Control Register
mr9: Reg<MR_SPEC>0x258 - Mode Register
sr9: Reg<SR_SPEC>0x25c - Status Register
ier9: Reg<IER_SPEC>0x260 - Interrupt Enable Register
idr9: Reg<IDR_SPEC>0x264 - Interrupt Disable Register
imr9: Reg<IMR_SPEC>0x268 - Interrupt Mask Register
isr9: Reg<ISR_SPEC>0x26c - Interrupt Status Register
mar10: Reg<MAR_SPEC>0x280 - Memory Address Register
psr10: Reg<PSR_SPEC>0x284 - Peripheral Select Register
tcr10: Reg<TCR_SPEC>0x288 - Transfer Counter Register
marr10: Reg<MARR_SPEC>0x28c - Memory Address Reload Register
tcrr10: Reg<TCRR_SPEC>0x290 - Transfer Counter Reload Register
cr10: Reg<CR_SPEC>0x294 - Control Register
mr10: Reg<MR_SPEC>0x298 - Mode Register
sr10: Reg<SR_SPEC>0x29c - Status Register
ier10: Reg<IER_SPEC>0x2a0 - Interrupt Enable Register
idr10: Reg<IDR_SPEC>0x2a4 - Interrupt Disable Register
imr10: Reg<IMR_SPEC>0x2a8 - Interrupt Mask Register
isr10: Reg<ISR_SPEC>0x2ac - Interrupt Status Register
mar11: Reg<MAR_SPEC>0x2c0 - Memory Address Register
psr11: Reg<PSR_SPEC>0x2c4 - Peripheral Select Register
tcr11: Reg<TCR_SPEC>0x2c8 - Transfer Counter Register
marr11: Reg<MARR_SPEC>0x2cc - Memory Address Reload Register
tcrr11: Reg<TCRR_SPEC>0x2d0 - Transfer Counter Reload Register
cr11: Reg<CR_SPEC>0x2d4 - Control Register
mr11: Reg<MR_SPEC>0x2d8 - Mode Register
sr11: Reg<SR_SPEC>0x2dc - Status Register
ier11: Reg<IER_SPEC>0x2e0 - Interrupt Enable Register
idr11: Reg<IDR_SPEC>0x2e4 - Interrupt Disable Register
imr11: Reg<IMR_SPEC>0x2e8 - Interrupt Mask Register
isr11: Reg<ISR_SPEC>0x2ec - Interrupt Status Register
mar12: Reg<MAR_SPEC>0x300 - Memory Address Register
psr12: Reg<PSR_SPEC>0x304 - Peripheral Select Register
tcr12: Reg<TCR_SPEC>0x308 - Transfer Counter Register
marr12: Reg<MARR_SPEC>0x30c - Memory Address Reload Register
tcrr12: Reg<TCRR_SPEC>0x310 - Transfer Counter Reload Register
cr12: Reg<CR_SPEC>0x314 - Control Register
mr12: Reg<MR_SPEC>0x318 - Mode Register
sr12: Reg<SR_SPEC>0x31c - Status Register
ier12: Reg<IER_SPEC>0x320 - Interrupt Enable Register
idr12: Reg<IDR_SPEC>0x324 - Interrupt Disable Register
imr12: Reg<IMR_SPEC>0x328 - Interrupt Mask Register
isr12: Reg<ISR_SPEC>0x32c - Interrupt Status Register
mar13: Reg<MAR_SPEC>0x340 - Memory Address Register
psr13: Reg<PSR_SPEC>0x344 - Peripheral Select Register
tcr13: Reg<TCR_SPEC>0x348 - Transfer Counter Register
marr13: Reg<MARR_SPEC>0x34c - Memory Address Reload Register
tcrr13: Reg<TCRR_SPEC>0x350 - Transfer Counter Reload Register
cr13: Reg<CR_SPEC>0x354 - Control Register
mr13: Reg<MR_SPEC>0x358 - Mode Register
sr13: Reg<SR_SPEC>0x35c - Status Register
ier13: Reg<IER_SPEC>0x360 - Interrupt Enable Register
idr13: Reg<IDR_SPEC>0x364 - Interrupt Disable Register
imr13: Reg<IMR_SPEC>0x368 - Interrupt Mask Register
isr13: Reg<ISR_SPEC>0x36c - Interrupt Status Register
mar14: Reg<MAR_SPEC>0x380 - Memory Address Register
psr14: Reg<PSR_SPEC>0x384 - Peripheral Select Register
tcr14: Reg<TCR_SPEC>0x388 - Transfer Counter Register
marr14: Reg<MARR_SPEC>0x38c - Memory Address Reload Register
tcrr14: Reg<TCRR_SPEC>0x390 - Transfer Counter Reload Register
cr14: Reg<CR_SPEC>0x394 - Control Register
mr14: Reg<MR_SPEC>0x398 - Mode Register
sr14: Reg<SR_SPEC>0x39c - Status Register
ier14: Reg<IER_SPEC>0x3a0 - Interrupt Enable Register
idr14: Reg<IDR_SPEC>0x3a4 - Interrupt Disable Register
imr14: Reg<IMR_SPEC>0x3a8 - Interrupt Mask Register
isr14: Reg<ISR_SPEC>0x3ac - Interrupt Status Register
mar15: Reg<MAR_SPEC>0x3c0 - Memory Address Register
psr15: Reg<PSR_SPEC>0x3c4 - Peripheral Select Register
tcr15: Reg<TCR_SPEC>0x3c8 - Transfer Counter Register
marr15: Reg<MARR_SPEC>0x3cc - Memory Address Reload Register
tcrr15: Reg<TCRR_SPEC>0x3d0 - Transfer Counter Reload Register
cr15: Reg<CR_SPEC>0x3d4 - Control Register
mr15: Reg<MR_SPEC>0x3d8 - Mode Register
sr15: Reg<SR_SPEC>0x3dc - Status Register
ier15: Reg<IER_SPEC>0x3e0 - Interrupt Enable Register
idr15: Reg<IDR_SPEC>0x3e4 - Interrupt Disable Register
imr15: Reg<IMR_SPEC>0x3e8 - Interrupt Mask Register
isr15: Reg<ISR_SPEC>0x3ec - Interrupt Status Register
pcontrol: Reg<PCONTROL_SPEC>0x800 - Performance Control Register
prdata0: Reg<PRDATA0_SPEC>0x804 - Channel 0 Read Data Cycles
prstall0: Reg<PRSTALL0_SPEC>0x808 - Channel 0 Read Stall Cycles
prlat0: Reg<PRLAT0_SPEC>0x80c - Channel 0 Read Max Latency
pwdata0: Reg<PWDATA0_SPEC>0x810 - Channel 0 Write Data Cycles
pwstall0: Reg<PWSTALL0_SPEC>0x814 - Channel 0 Write Stall Cycles
pwlat0: Reg<PWLAT0_SPEC>0x818 - Channel0 Write Max Latency
prdata1: Reg<PRDATA1_SPEC>0x81c - Channel 1 Read Data Cycles
prstall1: Reg<PRSTALL1_SPEC>0x820 - Channel Read Stall Cycles
prlat1: Reg<PRLAT1_SPEC>0x824 - Channel 1 Read Max Latency
pwdata1: Reg<PWDATA1_SPEC>0x828 - Channel 1 Write Data Cycles
pwstall1: Reg<PWSTALL1_SPEC>0x82c - Channel 1 Write stall Cycles
pwlat1: Reg<PWLAT1_SPEC>0x830 - Channel 1 Read Max Latency
version: Reg<VERSION_SPEC>0x834 - Version Register