Struct atsam4lc8b_pac::gpio::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 249 fields
pub gper0: Reg<GPER_SPEC>,
pub gpers0: Reg<GPERS_SPEC>,
pub gperc0: Reg<GPERC_SPEC>,
pub gpert0: Reg<GPERT_SPEC>,
pub pmr00: Reg<PMR0_SPEC>,
pub pmr0s0: Reg<PMR0S_SPEC>,
pub pmr0c0: Reg<PMR0C_SPEC>,
pub pmr0t0: Reg<PMR0T_SPEC>,
pub pmr10: Reg<PMR1_SPEC>,
pub pmr1s0: Reg<PMR1S_SPEC>,
pub pmr1c0: Reg<PMR1C_SPEC>,
pub pmr1t0: Reg<PMR1T_SPEC>,
pub pmr20: Reg<PMR2_SPEC>,
pub pmr2s0: Reg<PMR2S_SPEC>,
pub pmr2c0: Reg<PMR2C_SPEC>,
pub pmr2t0: Reg<PMR2T_SPEC>,
pub oder0: Reg<ODER_SPEC>,
pub oders0: Reg<ODERS_SPEC>,
pub oderc0: Reg<ODERC_SPEC>,
pub odert0: Reg<ODERT_SPEC>,
pub ovr0: Reg<OVR_SPEC>,
pub ovrs0: Reg<OVRS_SPEC>,
pub ovrc0: Reg<OVRC_SPEC>,
pub ovrt0: Reg<OVRT_SPEC>,
pub pvr0: Reg<PVR_SPEC>,
pub puer0: Reg<PUER_SPEC>,
pub puers0: Reg<PUERS_SPEC>,
pub puerc0: Reg<PUERC_SPEC>,
pub puert0: Reg<PUERT_SPEC>,
pub pder0: Reg<PDER_SPEC>,
pub pders0: Reg<PDERS_SPEC>,
pub pderc0: Reg<PDERC_SPEC>,
pub pdert0: Reg<PDERT_SPEC>,
pub ier0: Reg<IER_SPEC>,
pub iers0: Reg<IERS_SPEC>,
pub ierc0: Reg<IERC_SPEC>,
pub iert0: Reg<IERT_SPEC>,
pub imr00: Reg<IMR0_SPEC>,
pub imr0s0: Reg<IMR0S_SPEC>,
pub imr0c0: Reg<IMR0C_SPEC>,
pub imr0t0: Reg<IMR0T_SPEC>,
pub imr10: Reg<IMR1_SPEC>,
pub imr1s0: Reg<IMR1S_SPEC>,
pub imr1c0: Reg<IMR1C_SPEC>,
pub imr1t0: Reg<IMR1T_SPEC>,
pub gfer0: Reg<GFER_SPEC>,
pub gfers0: Reg<GFERS_SPEC>,
pub gferc0: Reg<GFERC_SPEC>,
pub gfert0: Reg<GFERT_SPEC>,
pub ifr0: Reg<IFR_SPEC>,
pub ifrc0: Reg<IFRC_SPEC>,
pub odmer0: Reg<ODMER_SPEC>,
pub odmers0: Reg<ODMERS_SPEC>,
pub odmerc0: Reg<ODMERC_SPEC>,
pub odmert0: Reg<ODMERT_SPEC>,
pub odcr00: Reg<ODCR0_SPEC>,
pub odcr0s0: Reg<ODCR0S_SPEC>,
pub odcr0c0: Reg<ODCR0C_SPEC>,
pub odcr0t0: Reg<ODCR0T_SPEC>,
pub odcr10: Reg<ODCR1_SPEC>,
pub odcr1s0: Reg<ODCR1S_SPEC>,
pub odcr1c0: Reg<ODCR1C_SPEC>,
pub odcr1t0: Reg<ODCR1T_SPEC>,
pub osrr00: Reg<OSRR0_SPEC>,
pub osrr0s0: Reg<OSRR0S_SPEC>,
pub osrr0c0: Reg<OSRR0C_SPEC>,
pub osrr0t0: Reg<OSRR0T_SPEC>,
pub ster0: Reg<STER_SPEC>,
pub sters0: Reg<STERS_SPEC>,
pub sterc0: Reg<STERC_SPEC>,
pub stert0: Reg<STERT_SPEC>,
pub ever0: Reg<EVER_SPEC>,
pub evers0: Reg<EVERS_SPEC>,
pub everc0: Reg<EVERC_SPEC>,
pub evert0: Reg<EVERT_SPEC>,
pub lock0: Reg<LOCK_SPEC>,
pub locks0: Reg<LOCKS_SPEC>,
pub lockc0: Reg<LOCKC_SPEC>,
pub lockt0: Reg<LOCKT_SPEC>,
pub unlock0: Reg<UNLOCK_SPEC>,
pub asr0: Reg<ASR_SPEC>,
pub parameter0: Reg<PARAMETER_SPEC>,
pub version0: Reg<VERSION_SPEC>,
pub gper1: Reg<GPER_SPEC>,
pub gpers1: Reg<GPERS_SPEC>,
pub gperc1: Reg<GPERC_SPEC>,
pub gpert1: Reg<GPERT_SPEC>,
pub pmr01: Reg<PMR0_SPEC>,
pub pmr0s1: Reg<PMR0S_SPEC>,
pub pmr0c1: Reg<PMR0C_SPEC>,
pub pmr0t1: Reg<PMR0T_SPEC>,
pub pmr11: Reg<PMR1_SPEC>,
pub pmr1s1: Reg<PMR1S_SPEC>,
pub pmr1c1: Reg<PMR1C_SPEC>,
pub pmr1t1: Reg<PMR1T_SPEC>,
pub pmr21: Reg<PMR2_SPEC>,
pub pmr2s1: Reg<PMR2S_SPEC>,
pub pmr2c1: Reg<PMR2C_SPEC>,
pub pmr2t1: Reg<PMR2T_SPEC>,
pub oder1: Reg<ODER_SPEC>,
pub oders1: Reg<ODERS_SPEC>,
pub oderc1: Reg<ODERC_SPEC>,
pub odert1: Reg<ODERT_SPEC>,
pub ovr1: Reg<OVR_SPEC>,
pub ovrs1: Reg<OVRS_SPEC>,
pub ovrc1: Reg<OVRC_SPEC>,
pub ovrt1: Reg<OVRT_SPEC>,
pub pvr1: Reg<PVR_SPEC>,
pub puer1: Reg<PUER_SPEC>,
pub puers1: Reg<PUERS_SPEC>,
pub puerc1: Reg<PUERC_SPEC>,
pub puert1: Reg<PUERT_SPEC>,
pub pder1: Reg<PDER_SPEC>,
pub pders1: Reg<PDERS_SPEC>,
pub pderc1: Reg<PDERC_SPEC>,
pub pdert1: Reg<PDERT_SPEC>,
pub ier1: Reg<IER_SPEC>,
pub iers1: Reg<IERS_SPEC>,
pub ierc1: Reg<IERC_SPEC>,
pub iert1: Reg<IERT_SPEC>,
pub imr01: Reg<IMR0_SPEC>,
pub imr0s1: Reg<IMR0S_SPEC>,
pub imr0c1: Reg<IMR0C_SPEC>,
pub imr0t1: Reg<IMR0T_SPEC>,
pub imr11: Reg<IMR1_SPEC>,
pub imr1s1: Reg<IMR1S_SPEC>,
pub imr1c1: Reg<IMR1C_SPEC>,
pub imr1t1: Reg<IMR1T_SPEC>,
pub gfer1: Reg<GFER_SPEC>,
pub gfers1: Reg<GFERS_SPEC>,
pub gferc1: Reg<GFERC_SPEC>,
pub gfert1: Reg<GFERT_SPEC>,
pub ifr1: Reg<IFR_SPEC>,
pub ifrc1: Reg<IFRC_SPEC>,
pub odmer1: Reg<ODMER_SPEC>,
pub odmers1: Reg<ODMERS_SPEC>,
pub odmerc1: Reg<ODMERC_SPEC>,
pub odmert1: Reg<ODMERT_SPEC>,
pub odcr01: Reg<ODCR0_SPEC>,
pub odcr0s1: Reg<ODCR0S_SPEC>,
pub odcr0c1: Reg<ODCR0C_SPEC>,
pub odcr0t1: Reg<ODCR0T_SPEC>,
pub odcr11: Reg<ODCR1_SPEC>,
pub odcr1s1: Reg<ODCR1S_SPEC>,
pub odcr1c1: Reg<ODCR1C_SPEC>,
pub odcr1t1: Reg<ODCR1T_SPEC>,
pub osrr01: Reg<OSRR0_SPEC>,
pub osrr0s1: Reg<OSRR0S_SPEC>,
pub osrr0c1: Reg<OSRR0C_SPEC>,
pub osrr0t1: Reg<OSRR0T_SPEC>,
pub ster1: Reg<STER_SPEC>,
pub sters1: Reg<STERS_SPEC>,
pub sterc1: Reg<STERC_SPEC>,
pub stert1: Reg<STERT_SPEC>,
pub ever1: Reg<EVER_SPEC>,
pub evers1: Reg<EVERS_SPEC>,
pub everc1: Reg<EVERC_SPEC>,
pub evert1: Reg<EVERT_SPEC>,
pub lock1: Reg<LOCK_SPEC>,
pub locks1: Reg<LOCKS_SPEC>,
pub lockc1: Reg<LOCKC_SPEC>,
pub lockt1: Reg<LOCKT_SPEC>,
pub unlock1: Reg<UNLOCK_SPEC>,
pub asr1: Reg<ASR_SPEC>,
pub parameter1: Reg<PARAMETER_SPEC>,
pub version1: Reg<VERSION_SPEC>,
pub gper2: Reg<GPER_SPEC>,
pub gpers2: Reg<GPERS_SPEC>,
pub gperc2: Reg<GPERC_SPEC>,
pub gpert2: Reg<GPERT_SPEC>,
pub pmr02: Reg<PMR0_SPEC>,
pub pmr0s2: Reg<PMR0S_SPEC>,
pub pmr0c2: Reg<PMR0C_SPEC>,
pub pmr0t2: Reg<PMR0T_SPEC>,
pub pmr12: Reg<PMR1_SPEC>,
pub pmr1s2: Reg<PMR1S_SPEC>,
pub pmr1c2: Reg<PMR1C_SPEC>,
pub pmr1t2: Reg<PMR1T_SPEC>,
pub pmr22: Reg<PMR2_SPEC>,
pub pmr2s2: Reg<PMR2S_SPEC>,
pub pmr2c2: Reg<PMR2C_SPEC>,
pub pmr2t2: Reg<PMR2T_SPEC>,
pub oder2: Reg<ODER_SPEC>,
pub oders2: Reg<ODERS_SPEC>,
pub oderc2: Reg<ODERC_SPEC>,
pub odert2: Reg<ODERT_SPEC>,
pub ovr2: Reg<OVR_SPEC>,
pub ovrs2: Reg<OVRS_SPEC>,
pub ovrc2: Reg<OVRC_SPEC>,
pub ovrt2: Reg<OVRT_SPEC>,
pub pvr2: Reg<PVR_SPEC>,
pub puer2: Reg<PUER_SPEC>,
pub puers2: Reg<PUERS_SPEC>,
pub puerc2: Reg<PUERC_SPEC>,
pub puert2: Reg<PUERT_SPEC>,
pub pder2: Reg<PDER_SPEC>,
pub pders2: Reg<PDERS_SPEC>,
pub pderc2: Reg<PDERC_SPEC>,
pub pdert2: Reg<PDERT_SPEC>,
pub ier2: Reg<IER_SPEC>,
pub iers2: Reg<IERS_SPEC>,
pub ierc2: Reg<IERC_SPEC>,
pub iert2: Reg<IERT_SPEC>,
pub imr02: Reg<IMR0_SPEC>,
pub imr0s2: Reg<IMR0S_SPEC>,
pub imr0c2: Reg<IMR0C_SPEC>,
pub imr0t2: Reg<IMR0T_SPEC>,
pub imr12: Reg<IMR1_SPEC>,
pub imr1s2: Reg<IMR1S_SPEC>,
pub imr1c2: Reg<IMR1C_SPEC>,
pub imr1t2: Reg<IMR1T_SPEC>,
pub gfer2: Reg<GFER_SPEC>,
pub gfers2: Reg<GFERS_SPEC>,
pub gferc2: Reg<GFERC_SPEC>,
pub gfert2: Reg<GFERT_SPEC>,
pub ifr2: Reg<IFR_SPEC>,
pub ifrc2: Reg<IFRC_SPEC>,
pub odmer2: Reg<ODMER_SPEC>,
pub odmers2: Reg<ODMERS_SPEC>,
pub odmerc2: Reg<ODMERC_SPEC>,
pub odmert2: Reg<ODMERT_SPEC>,
pub odcr02: Reg<ODCR0_SPEC>,
pub odcr0s2: Reg<ODCR0S_SPEC>,
pub odcr0c2: Reg<ODCR0C_SPEC>,
pub odcr0t2: Reg<ODCR0T_SPEC>,
pub odcr12: Reg<ODCR1_SPEC>,
pub odcr1s2: Reg<ODCR1S_SPEC>,
pub odcr1c2: Reg<ODCR1C_SPEC>,
pub odcr1t2: Reg<ODCR1T_SPEC>,
pub osrr02: Reg<OSRR0_SPEC>,
pub osrr0s2: Reg<OSRR0S_SPEC>,
pub osrr0c2: Reg<OSRR0C_SPEC>,
pub osrr0t2: Reg<OSRR0T_SPEC>,
pub ster2: Reg<STER_SPEC>,
pub sters2: Reg<STERS_SPEC>,
pub sterc2: Reg<STERC_SPEC>,
pub stert2: Reg<STERT_SPEC>,
pub ever2: Reg<EVER_SPEC>,
pub evers2: Reg<EVERS_SPEC>,
pub everc2: Reg<EVERC_SPEC>,
pub evert2: Reg<EVERT_SPEC>,
pub lock2: Reg<LOCK_SPEC>,
pub locks2: Reg<LOCKS_SPEC>,
pub lockc2: Reg<LOCKC_SPEC>,
pub lockt2: Reg<LOCKT_SPEC>,
pub unlock2: Reg<UNLOCK_SPEC>,
pub asr2: Reg<ASR_SPEC>,
pub parameter2: Reg<PARAMETER_SPEC>,
pub version2: Reg<VERSION_SPEC>,
// some fields omitted
}Expand description
Register block
Fields
gper0: Reg<GPER_SPEC>0x00 - GPIO Enable Register
gpers0: Reg<GPERS_SPEC>0x04 - GPIO Enable Register - Set
gperc0: Reg<GPERC_SPEC>0x08 - GPIO Enable Register - Clear
gpert0: Reg<GPERT_SPEC>0x0c - GPIO Enable Register - Toggle
pmr00: Reg<PMR0_SPEC>0x10 - Peripheral Mux Register 0
pmr0s0: Reg<PMR0S_SPEC>0x14 - Peripheral Mux Register 0 - Set
pmr0c0: Reg<PMR0C_SPEC>0x18 - Peripheral Mux Register 0 - Clear
pmr0t0: Reg<PMR0T_SPEC>0x1c - Peripheral Mux Register 0 - Toggle
pmr10: Reg<PMR1_SPEC>0x20 - Peripheral Mux Register 1
pmr1s0: Reg<PMR1S_SPEC>0x24 - Peripheral Mux Register 1 - Set
pmr1c0: Reg<PMR1C_SPEC>0x28 - Peripheral Mux Register 1 - Clear
pmr1t0: Reg<PMR1T_SPEC>0x2c - Peripheral Mux Register 1 - Toggle
pmr20: Reg<PMR2_SPEC>0x30 - Peripheral Mux Register 2
pmr2s0: Reg<PMR2S_SPEC>0x34 - Peripheral Mux Register 2 - Set
pmr2c0: Reg<PMR2C_SPEC>0x38 - Peripheral Mux Register 2 - Clear
pmr2t0: Reg<PMR2T_SPEC>0x3c - Peripheral Mux Register 2 - Toggle
oder0: Reg<ODER_SPEC>0x40 - Output Driver Enable Register
oders0: Reg<ODERS_SPEC>0x44 - Output Driver Enable Register - Set
oderc0: Reg<ODERC_SPEC>0x48 - Output Driver Enable Register - Clear
odert0: Reg<ODERT_SPEC>0x4c - Output Driver Enable Register - Toggle
ovr0: Reg<OVR_SPEC>0x50 - Output Value Register
ovrs0: Reg<OVRS_SPEC>0x54 - Output Value Register - Set
ovrc0: Reg<OVRC_SPEC>0x58 - Output Value Register - Clear
ovrt0: Reg<OVRT_SPEC>0x5c - Output Value Register - Toggle
pvr0: Reg<PVR_SPEC>0x60 - Pin Value Register
puer0: Reg<PUER_SPEC>0x70 - Pull-up Enable Register
puers0: Reg<PUERS_SPEC>0x74 - Pull-up Enable Register - Set
puerc0: Reg<PUERC_SPEC>0x78 - Pull-up Enable Register - Clear
puert0: Reg<PUERT_SPEC>0x7c - Pull-up Enable Register - Toggle
pder0: Reg<PDER_SPEC>0x80 - Pull-down Enable Register
pders0: Reg<PDERS_SPEC>0x84 - Pull-down Enable Register - Set
pderc0: Reg<PDERC_SPEC>0x88 - Pull-down Enable Register - Clear
pdert0: Reg<PDERT_SPEC>0x8c - Pull-down Enable Register - Toggle
ier0: Reg<IER_SPEC>0x90 - Interrupt Enable Register
iers0: Reg<IERS_SPEC>0x94 - Interrupt Enable Register - Set
ierc0: Reg<IERC_SPEC>0x98 - Interrupt Enable Register - Clear
iert0: Reg<IERT_SPEC>0x9c - Interrupt Enable Register - Toggle
imr00: Reg<IMR0_SPEC>0xa0 - Interrupt Mode Register 0
imr0s0: Reg<IMR0S_SPEC>0xa4 - Interrupt Mode Register 0 - Set
imr0c0: Reg<IMR0C_SPEC>0xa8 - Interrupt Mode Register 0 - Clear
imr0t0: Reg<IMR0T_SPEC>0xac - Interrupt Mode Register 0 - Toggle
imr10: Reg<IMR1_SPEC>0xb0 - Interrupt Mode Register 1
imr1s0: Reg<IMR1S_SPEC>0xb4 - Interrupt Mode Register 1 - Set
imr1c0: Reg<IMR1C_SPEC>0xb8 - Interrupt Mode Register 1 - Clear
imr1t0: Reg<IMR1T_SPEC>0xbc - Interrupt Mode Register 1 - Toggle
gfer0: Reg<GFER_SPEC>0xc0 - Glitch Filter Enable Register
gfers0: Reg<GFERS_SPEC>0xc4 - Glitch Filter Enable Register - Set
gferc0: Reg<GFERC_SPEC>0xc8 - Glitch Filter Enable Register - Clear
gfert0: Reg<GFERT_SPEC>0xcc - Glitch Filter Enable Register - Toggle
ifr0: Reg<IFR_SPEC>0xd0 - Interrupt Flag Register
ifrc0: Reg<IFRC_SPEC>0xd8 - Interrupt Flag Register - Clear
odmer0: Reg<ODMER_SPEC>0xe0 - Open Drain Mode Register
odmers0: Reg<ODMERS_SPEC>0xe4 - Open Drain Mode Register - Set
odmerc0: Reg<ODMERC_SPEC>0xe8 - Open Drain Mode Register - Clear
odmert0: Reg<ODMERT_SPEC>0xec - Open Drain Mode Register - Toggle
odcr00: Reg<ODCR0_SPEC>0x100 - Output Driving Capability Register 0
odcr0s0: Reg<ODCR0S_SPEC>0x104 - Output Driving Capability Register 0 - Set
odcr0c0: Reg<ODCR0C_SPEC>0x108 - Output Driving Capability Register 0 - Clear
odcr0t0: Reg<ODCR0T_SPEC>0x10c - Output Driving Capability Register 0 - Toggle
odcr10: Reg<ODCR1_SPEC>0x110 - Output Driving Capability Register 1
odcr1s0: Reg<ODCR1S_SPEC>0x114 - Output Driving Capability Register 1 - Set
odcr1c0: Reg<ODCR1C_SPEC>0x118 - Output Driving Capability Register 1 - Clear
odcr1t0: Reg<ODCR1T_SPEC>0x11c - Output Driving Capability Register 1 - Toggle
osrr00: Reg<OSRR0_SPEC>0x130 - Output Slew Rate Register 0
osrr0s0: Reg<OSRR0S_SPEC>0x134 - Output Slew Rate Register 0 - Set
osrr0c0: Reg<OSRR0C_SPEC>0x138 - Output Slew Rate Register 0 - Clear
osrr0t0: Reg<OSRR0T_SPEC>0x13c - Output Slew Rate Register 0 - Toggle
ster0: Reg<STER_SPEC>0x160 - Schmitt Trigger Enable Register
sters0: Reg<STERS_SPEC>0x164 - Schmitt Trigger Enable Register - Set
sterc0: Reg<STERC_SPEC>0x168 - Schmitt Trigger Enable Register - Clear
stert0: Reg<STERT_SPEC>0x16c - Schmitt Trigger Enable Register - Toggle
ever0: Reg<EVER_SPEC>0x180 - Event Enable Register
evers0: Reg<EVERS_SPEC>0x184 - Event Enable Register - Set
everc0: Reg<EVERC_SPEC>0x188 - Event Enable Register - Clear
evert0: Reg<EVERT_SPEC>0x18c - Event Enable Register - Toggle
lock0: Reg<LOCK_SPEC>0x1a0 - Lock Register
locks0: Reg<LOCKS_SPEC>0x1a4 - Lock Register - Set
lockc0: Reg<LOCKC_SPEC>0x1a8 - Lock Register - Clear
lockt0: Reg<LOCKT_SPEC>0x1ac - Lock Register - Toggle
unlock0: Reg<UNLOCK_SPEC>0x1e0 - Unlock Register
asr0: Reg<ASR_SPEC>0x1e4 - Access Status Register
parameter0: Reg<PARAMETER_SPEC>0x1f8 - Parameter Register
version0: Reg<VERSION_SPEC>0x1fc - Version Register
gper1: Reg<GPER_SPEC>0x200 - GPIO Enable Register
gpers1: Reg<GPERS_SPEC>0x204 - GPIO Enable Register - Set
gperc1: Reg<GPERC_SPEC>0x208 - GPIO Enable Register - Clear
gpert1: Reg<GPERT_SPEC>0x20c - GPIO Enable Register - Toggle
pmr01: Reg<PMR0_SPEC>0x210 - Peripheral Mux Register 0
pmr0s1: Reg<PMR0S_SPEC>0x214 - Peripheral Mux Register 0 - Set
pmr0c1: Reg<PMR0C_SPEC>0x218 - Peripheral Mux Register 0 - Clear
pmr0t1: Reg<PMR0T_SPEC>0x21c - Peripheral Mux Register 0 - Toggle
pmr11: Reg<PMR1_SPEC>0x220 - Peripheral Mux Register 1
pmr1s1: Reg<PMR1S_SPEC>0x224 - Peripheral Mux Register 1 - Set
pmr1c1: Reg<PMR1C_SPEC>0x228 - Peripheral Mux Register 1 - Clear
pmr1t1: Reg<PMR1T_SPEC>0x22c - Peripheral Mux Register 1 - Toggle
pmr21: Reg<PMR2_SPEC>0x230 - Peripheral Mux Register 2
pmr2s1: Reg<PMR2S_SPEC>0x234 - Peripheral Mux Register 2 - Set
pmr2c1: Reg<PMR2C_SPEC>0x238 - Peripheral Mux Register 2 - Clear
pmr2t1: Reg<PMR2T_SPEC>0x23c - Peripheral Mux Register 2 - Toggle
oder1: Reg<ODER_SPEC>0x240 - Output Driver Enable Register
oders1: Reg<ODERS_SPEC>0x244 - Output Driver Enable Register - Set
oderc1: Reg<ODERC_SPEC>0x248 - Output Driver Enable Register - Clear
odert1: Reg<ODERT_SPEC>0x24c - Output Driver Enable Register - Toggle
ovr1: Reg<OVR_SPEC>0x250 - Output Value Register
ovrs1: Reg<OVRS_SPEC>0x254 - Output Value Register - Set
ovrc1: Reg<OVRC_SPEC>0x258 - Output Value Register - Clear
ovrt1: Reg<OVRT_SPEC>0x25c - Output Value Register - Toggle
pvr1: Reg<PVR_SPEC>0x260 - Pin Value Register
puer1: Reg<PUER_SPEC>0x270 - Pull-up Enable Register
puers1: Reg<PUERS_SPEC>0x274 - Pull-up Enable Register - Set
puerc1: Reg<PUERC_SPEC>0x278 - Pull-up Enable Register - Clear
puert1: Reg<PUERT_SPEC>0x27c - Pull-up Enable Register - Toggle
pder1: Reg<PDER_SPEC>0x280 - Pull-down Enable Register
pders1: Reg<PDERS_SPEC>0x284 - Pull-down Enable Register - Set
pderc1: Reg<PDERC_SPEC>0x288 - Pull-down Enable Register - Clear
pdert1: Reg<PDERT_SPEC>0x28c - Pull-down Enable Register - Toggle
ier1: Reg<IER_SPEC>0x290 - Interrupt Enable Register
iers1: Reg<IERS_SPEC>0x294 - Interrupt Enable Register - Set
ierc1: Reg<IERC_SPEC>0x298 - Interrupt Enable Register - Clear
iert1: Reg<IERT_SPEC>0x29c - Interrupt Enable Register - Toggle
imr01: Reg<IMR0_SPEC>0x2a0 - Interrupt Mode Register 0
imr0s1: Reg<IMR0S_SPEC>0x2a4 - Interrupt Mode Register 0 - Set
imr0c1: Reg<IMR0C_SPEC>0x2a8 - Interrupt Mode Register 0 - Clear
imr0t1: Reg<IMR0T_SPEC>0x2ac - Interrupt Mode Register 0 - Toggle
imr11: Reg<IMR1_SPEC>0x2b0 - Interrupt Mode Register 1
imr1s1: Reg<IMR1S_SPEC>0x2b4 - Interrupt Mode Register 1 - Set
imr1c1: Reg<IMR1C_SPEC>0x2b8 - Interrupt Mode Register 1 - Clear
imr1t1: Reg<IMR1T_SPEC>0x2bc - Interrupt Mode Register 1 - Toggle
gfer1: Reg<GFER_SPEC>0x2c0 - Glitch Filter Enable Register
gfers1: Reg<GFERS_SPEC>0x2c4 - Glitch Filter Enable Register - Set
gferc1: Reg<GFERC_SPEC>0x2c8 - Glitch Filter Enable Register - Clear
gfert1: Reg<GFERT_SPEC>0x2cc - Glitch Filter Enable Register - Toggle
ifr1: Reg<IFR_SPEC>0x2d0 - Interrupt Flag Register
ifrc1: Reg<IFRC_SPEC>0x2d8 - Interrupt Flag Register - Clear
odmer1: Reg<ODMER_SPEC>0x2e0 - Open Drain Mode Register
odmers1: Reg<ODMERS_SPEC>0x2e4 - Open Drain Mode Register - Set
odmerc1: Reg<ODMERC_SPEC>0x2e8 - Open Drain Mode Register - Clear
odmert1: Reg<ODMERT_SPEC>0x2ec - Open Drain Mode Register - Toggle
odcr01: Reg<ODCR0_SPEC>0x300 - Output Driving Capability Register 0
odcr0s1: Reg<ODCR0S_SPEC>0x304 - Output Driving Capability Register 0 - Set
odcr0c1: Reg<ODCR0C_SPEC>0x308 - Output Driving Capability Register 0 - Clear
odcr0t1: Reg<ODCR0T_SPEC>0x30c - Output Driving Capability Register 0 - Toggle
odcr11: Reg<ODCR1_SPEC>0x310 - Output Driving Capability Register 1
odcr1s1: Reg<ODCR1S_SPEC>0x314 - Output Driving Capability Register 1 - Set
odcr1c1: Reg<ODCR1C_SPEC>0x318 - Output Driving Capability Register 1 - Clear
odcr1t1: Reg<ODCR1T_SPEC>0x31c - Output Driving Capability Register 1 - Toggle
osrr01: Reg<OSRR0_SPEC>0x330 - Output Slew Rate Register 0
osrr0s1: Reg<OSRR0S_SPEC>0x334 - Output Slew Rate Register 0 - Set
osrr0c1: Reg<OSRR0C_SPEC>0x338 - Output Slew Rate Register 0 - Clear
osrr0t1: Reg<OSRR0T_SPEC>0x33c - Output Slew Rate Register 0 - Toggle
ster1: Reg<STER_SPEC>0x360 - Schmitt Trigger Enable Register
sters1: Reg<STERS_SPEC>0x364 - Schmitt Trigger Enable Register - Set
sterc1: Reg<STERC_SPEC>0x368 - Schmitt Trigger Enable Register - Clear
stert1: Reg<STERT_SPEC>0x36c - Schmitt Trigger Enable Register - Toggle
ever1: Reg<EVER_SPEC>0x380 - Event Enable Register
evers1: Reg<EVERS_SPEC>0x384 - Event Enable Register - Set
everc1: Reg<EVERC_SPEC>0x388 - Event Enable Register - Clear
evert1: Reg<EVERT_SPEC>0x38c - Event Enable Register - Toggle
lock1: Reg<LOCK_SPEC>0x3a0 - Lock Register
locks1: Reg<LOCKS_SPEC>0x3a4 - Lock Register - Set
lockc1: Reg<LOCKC_SPEC>0x3a8 - Lock Register - Clear
lockt1: Reg<LOCKT_SPEC>0x3ac - Lock Register - Toggle
unlock1: Reg<UNLOCK_SPEC>0x3e0 - Unlock Register
asr1: Reg<ASR_SPEC>0x3e4 - Access Status Register
parameter1: Reg<PARAMETER_SPEC>0x3f8 - Parameter Register
version1: Reg<VERSION_SPEC>0x3fc - Version Register
gper2: Reg<GPER_SPEC>0x400 - GPIO Enable Register
gpers2: Reg<GPERS_SPEC>0x404 - GPIO Enable Register - Set
gperc2: Reg<GPERC_SPEC>0x408 - GPIO Enable Register - Clear
gpert2: Reg<GPERT_SPEC>0x40c - GPIO Enable Register - Toggle
pmr02: Reg<PMR0_SPEC>0x410 - Peripheral Mux Register 0
pmr0s2: Reg<PMR0S_SPEC>0x414 - Peripheral Mux Register 0 - Set
pmr0c2: Reg<PMR0C_SPEC>0x418 - Peripheral Mux Register 0 - Clear
pmr0t2: Reg<PMR0T_SPEC>0x41c - Peripheral Mux Register 0 - Toggle
pmr12: Reg<PMR1_SPEC>0x420 - Peripheral Mux Register 1
pmr1s2: Reg<PMR1S_SPEC>0x424 - Peripheral Mux Register 1 - Set
pmr1c2: Reg<PMR1C_SPEC>0x428 - Peripheral Mux Register 1 - Clear
pmr1t2: Reg<PMR1T_SPEC>0x42c - Peripheral Mux Register 1 - Toggle
pmr22: Reg<PMR2_SPEC>0x430 - Peripheral Mux Register 2
pmr2s2: Reg<PMR2S_SPEC>0x434 - Peripheral Mux Register 2 - Set
pmr2c2: Reg<PMR2C_SPEC>0x438 - Peripheral Mux Register 2 - Clear
pmr2t2: Reg<PMR2T_SPEC>0x43c - Peripheral Mux Register 2 - Toggle
oder2: Reg<ODER_SPEC>0x440 - Output Driver Enable Register
oders2: Reg<ODERS_SPEC>0x444 - Output Driver Enable Register - Set
oderc2: Reg<ODERC_SPEC>0x448 - Output Driver Enable Register - Clear
odert2: Reg<ODERT_SPEC>0x44c - Output Driver Enable Register - Toggle
ovr2: Reg<OVR_SPEC>0x450 - Output Value Register
ovrs2: Reg<OVRS_SPEC>0x454 - Output Value Register - Set
ovrc2: Reg<OVRC_SPEC>0x458 - Output Value Register - Clear
ovrt2: Reg<OVRT_SPEC>0x45c - Output Value Register - Toggle
pvr2: Reg<PVR_SPEC>0x460 - Pin Value Register
puer2: Reg<PUER_SPEC>0x470 - Pull-up Enable Register
puers2: Reg<PUERS_SPEC>0x474 - Pull-up Enable Register - Set
puerc2: Reg<PUERC_SPEC>0x478 - Pull-up Enable Register - Clear
puert2: Reg<PUERT_SPEC>0x47c - Pull-up Enable Register - Toggle
pder2: Reg<PDER_SPEC>0x480 - Pull-down Enable Register
pders2: Reg<PDERS_SPEC>0x484 - Pull-down Enable Register - Set
pderc2: Reg<PDERC_SPEC>0x488 - Pull-down Enable Register - Clear
pdert2: Reg<PDERT_SPEC>0x48c - Pull-down Enable Register - Toggle
ier2: Reg<IER_SPEC>0x490 - Interrupt Enable Register
iers2: Reg<IERS_SPEC>0x494 - Interrupt Enable Register - Set
ierc2: Reg<IERC_SPEC>0x498 - Interrupt Enable Register - Clear
iert2: Reg<IERT_SPEC>0x49c - Interrupt Enable Register - Toggle
imr02: Reg<IMR0_SPEC>0x4a0 - Interrupt Mode Register 0
imr0s2: Reg<IMR0S_SPEC>0x4a4 - Interrupt Mode Register 0 - Set
imr0c2: Reg<IMR0C_SPEC>0x4a8 - Interrupt Mode Register 0 - Clear
imr0t2: Reg<IMR0T_SPEC>0x4ac - Interrupt Mode Register 0 - Toggle
imr12: Reg<IMR1_SPEC>0x4b0 - Interrupt Mode Register 1
imr1s2: Reg<IMR1S_SPEC>0x4b4 - Interrupt Mode Register 1 - Set
imr1c2: Reg<IMR1C_SPEC>0x4b8 - Interrupt Mode Register 1 - Clear
imr1t2: Reg<IMR1T_SPEC>0x4bc - Interrupt Mode Register 1 - Toggle
gfer2: Reg<GFER_SPEC>0x4c0 - Glitch Filter Enable Register
gfers2: Reg<GFERS_SPEC>0x4c4 - Glitch Filter Enable Register - Set
gferc2: Reg<GFERC_SPEC>0x4c8 - Glitch Filter Enable Register - Clear
gfert2: Reg<GFERT_SPEC>0x4cc - Glitch Filter Enable Register - Toggle
ifr2: Reg<IFR_SPEC>0x4d0 - Interrupt Flag Register
ifrc2: Reg<IFRC_SPEC>0x4d8 - Interrupt Flag Register - Clear
odmer2: Reg<ODMER_SPEC>0x4e0 - Open Drain Mode Register
odmers2: Reg<ODMERS_SPEC>0x4e4 - Open Drain Mode Register - Set
odmerc2: Reg<ODMERC_SPEC>0x4e8 - Open Drain Mode Register - Clear
odmert2: Reg<ODMERT_SPEC>0x4ec - Open Drain Mode Register - Toggle
odcr02: Reg<ODCR0_SPEC>0x500 - Output Driving Capability Register 0
odcr0s2: Reg<ODCR0S_SPEC>0x504 - Output Driving Capability Register 0 - Set
odcr0c2: Reg<ODCR0C_SPEC>0x508 - Output Driving Capability Register 0 - Clear
odcr0t2: Reg<ODCR0T_SPEC>0x50c - Output Driving Capability Register 0 - Toggle
odcr12: Reg<ODCR1_SPEC>0x510 - Output Driving Capability Register 1
odcr1s2: Reg<ODCR1S_SPEC>0x514 - Output Driving Capability Register 1 - Set
odcr1c2: Reg<ODCR1C_SPEC>0x518 - Output Driving Capability Register 1 - Clear
odcr1t2: Reg<ODCR1T_SPEC>0x51c - Output Driving Capability Register 1 - Toggle
osrr02: Reg<OSRR0_SPEC>0x530 - Output Slew Rate Register 0
osrr0s2: Reg<OSRR0S_SPEC>0x534 - Output Slew Rate Register 0 - Set
osrr0c2: Reg<OSRR0C_SPEC>0x538 - Output Slew Rate Register 0 - Clear
osrr0t2: Reg<OSRR0T_SPEC>0x53c - Output Slew Rate Register 0 - Toggle
ster2: Reg<STER_SPEC>0x560 - Schmitt Trigger Enable Register
sters2: Reg<STERS_SPEC>0x564 - Schmitt Trigger Enable Register - Set
sterc2: Reg<STERC_SPEC>0x568 - Schmitt Trigger Enable Register - Clear
stert2: Reg<STERT_SPEC>0x56c - Schmitt Trigger Enable Register - Toggle
ever2: Reg<EVER_SPEC>0x580 - Event Enable Register
evers2: Reg<EVERS_SPEC>0x584 - Event Enable Register - Set
everc2: Reg<EVERC_SPEC>0x588 - Event Enable Register - Clear
evert2: Reg<EVERT_SPEC>0x58c - Event Enable Register - Toggle
lock2: Reg<LOCK_SPEC>0x5a0 - Lock Register
locks2: Reg<LOCKS_SPEC>0x5a4 - Lock Register - Set
lockc2: Reg<LOCKC_SPEC>0x5a8 - Lock Register - Clear
lockt2: Reg<LOCKT_SPEC>0x5ac - Lock Register - Toggle
unlock2: Reg<UNLOCK_SPEC>0x5e0 - Unlock Register
asr2: Reg<ASR_SPEC>0x5e4 - Access Status Register
parameter2: Reg<PARAMETER_SPEC>0x5f8 - Parameter Register
version2: Reg<VERSION_SPEC>0x5fc - Version Register