Struct atsam4lc4c::pdca::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub mar0: MAR,
    pub psr0: PSR,
    pub tcr0: TCR,
    pub marr0: MARR,
    pub tcrr0: TCRR,
    pub cr0: CR,
    pub mr0: MR,
    pub sr0: SR,
    pub ier0: IER,
    pub idr0: IDR,
    pub imr0: IMR,
    pub isr0: ISR,
    pub mar1: MAR,
    pub psr1: PSR,
    pub tcr1: TCR,
    pub marr1: MARR,
    pub tcrr1: TCRR,
    pub cr1: CR,
    pub mr1: MR,
    pub sr1: SR,
    pub ier1: IER,
    pub idr1: IDR,
    pub imr1: IMR,
    pub isr1: ISR,
    pub mar2: MAR,
    pub psr2: PSR,
    pub tcr2: TCR,
    pub marr2: MARR,
    pub tcrr2: TCRR,
    pub cr2: CR,
    pub mr2: MR,
    pub sr2: SR,
    pub ier2: IER,
    pub idr2: IDR,
    pub imr2: IMR,
    pub isr2: ISR,
    pub mar3: MAR,
    pub psr3: PSR,
    pub tcr3: TCR,
    pub marr3: MARR,
    pub tcrr3: TCRR,
    pub cr3: CR,
    pub mr3: MR,
    pub sr3: SR,
    pub ier3: IER,
    pub idr3: IDR,
    pub imr3: IMR,
    pub isr3: ISR,
    pub mar4: MAR,
    pub psr4: PSR,
    pub tcr4: TCR,
    pub marr4: MARR,
    pub tcrr4: TCRR,
    pub cr4: CR,
    pub mr4: MR,
    pub sr4: SR,
    pub ier4: IER,
    pub idr4: IDR,
    pub imr4: IMR,
    pub isr4: ISR,
    pub mar5: MAR,
    pub psr5: PSR,
    pub tcr5: TCR,
    pub marr5: MARR,
    pub tcrr5: TCRR,
    pub cr5: CR,
    pub mr5: MR,
    pub sr5: SR,
    pub ier5: IER,
    pub idr5: IDR,
    pub imr5: IMR,
    pub isr5: ISR,
    pub mar6: MAR,
    pub psr6: PSR,
    pub tcr6: TCR,
    pub marr6: MARR,
    pub tcrr6: TCRR,
    pub cr6: CR,
    pub mr6: MR,
    pub sr6: SR,
    pub ier6: IER,
    pub idr6: IDR,
    pub imr6: IMR,
    pub isr6: ISR,
    pub mar7: MAR,
    pub psr7: PSR,
    pub tcr7: TCR,
    pub marr7: MARR,
    pub tcrr7: TCRR,
    pub cr7: CR,
    pub mr7: MR,
    pub sr7: SR,
    pub ier7: IER,
    pub idr7: IDR,
    pub imr7: IMR,
    pub isr7: ISR,
    pub mar8: MAR,
    pub psr8: PSR,
    pub tcr8: TCR,
    pub marr8: MARR,
    pub tcrr8: TCRR,
    pub cr8: CR,
    pub mr8: MR,
    pub sr8: SR,
    pub ier8: IER,
    pub idr8: IDR,
    pub imr8: IMR,
    pub isr8: ISR,
    pub mar9: MAR,
    pub psr9: PSR,
    pub tcr9: TCR,
    pub marr9: MARR,
    pub tcrr9: TCRR,
    pub cr9: CR,
    pub mr9: MR,
    pub sr9: SR,
    pub ier9: IER,
    pub idr9: IDR,
    pub imr9: IMR,
    pub isr9: ISR,
    pub mar10: MAR,
    pub psr10: PSR,
    pub tcr10: TCR,
    pub marr10: MARR,
    pub tcrr10: TCRR,
    pub cr10: CR,
    pub mr10: MR,
    pub sr10: SR,
    pub ier10: IER,
    pub idr10: IDR,
    pub imr10: IMR,
    pub isr10: ISR,
    pub mar11: MAR,
    pub psr11: PSR,
    pub tcr11: TCR,
    pub marr11: MARR,
    pub tcrr11: TCRR,
    pub cr11: CR,
    pub mr11: MR,
    pub sr11: SR,
    pub ier11: IER,
    pub idr11: IDR,
    pub imr11: IMR,
    pub isr11: ISR,
    pub mar12: MAR,
    pub psr12: PSR,
    pub tcr12: TCR,
    pub marr12: MARR,
    pub tcrr12: TCRR,
    pub cr12: CR,
    pub mr12: MR,
    pub sr12: SR,
    pub ier12: IER,
    pub idr12: IDR,
    pub imr12: IMR,
    pub isr12: ISR,
    pub mar13: MAR,
    pub psr13: PSR,
    pub tcr13: TCR,
    pub marr13: MARR,
    pub tcrr13: TCRR,
    pub cr13: CR,
    pub mr13: MR,
    pub sr13: SR,
    pub ier13: IER,
    pub idr13: IDR,
    pub imr13: IMR,
    pub isr13: ISR,
    pub mar14: MAR,
    pub psr14: PSR,
    pub tcr14: TCR,
    pub marr14: MARR,
    pub tcrr14: TCRR,
    pub cr14: CR,
    pub mr14: MR,
    pub sr14: SR,
    pub ier14: IER,
    pub idr14: IDR,
    pub imr14: IMR,
    pub isr14: ISR,
    pub mar15: MAR,
    pub psr15: PSR,
    pub tcr15: TCR,
    pub marr15: MARR,
    pub tcrr15: TCRR,
    pub cr15: CR,
    pub mr15: MR,
    pub sr15: SR,
    pub ier15: IER,
    pub idr15: IDR,
    pub imr15: IMR,
    pub isr15: ISR,
    pub pcontrol: PCONTROL,
    pub prdata0: PRDATA0,
    pub prstall0: PRSTALL0,
    pub prlat0: PRLAT0,
    pub pwdata0: PWDATA0,
    pub pwstall0: PWSTALL0,
    pub pwlat0: PWLAT0,
    pub prdata1: PRDATA1,
    pub prstall1: PRSTALL1,
    pub prlat1: PRLAT1,
    pub pwdata1: PWDATA1,
    pub pwstall1: PWSTALL1,
    pub pwlat1: PWLAT1,
    pub version: VERSION,
    // some fields omitted
}

Register block

Fields

mar0: MAR

0x00 - Memory Address Register

psr0: PSR

0x04 - Peripheral Select Register

tcr0: TCR

0x08 - Transfer Counter Register

marr0: MARR

0x0c - Memory Address Reload Register

tcrr0: TCRR

0x10 - Transfer Counter Reload Register

cr0: CR

0x14 - Control Register

mr0: MR

0x18 - Mode Register

sr0: SR

0x1c - Status Register

ier0: IER

0x20 - Interrupt Enable Register

idr0: IDR

0x24 - Interrupt Disable Register

imr0: IMR

0x28 - Interrupt Mask Register

isr0: ISR

0x2c - Interrupt Status Register

mar1: MAR

0x40 - Memory Address Register

psr1: PSR

0x44 - Peripheral Select Register

tcr1: TCR

0x48 - Transfer Counter Register

marr1: MARR

0x4c - Memory Address Reload Register

tcrr1: TCRR

0x50 - Transfer Counter Reload Register

cr1: CR

0x54 - Control Register

mr1: MR

0x58 - Mode Register

sr1: SR

0x5c - Status Register

ier1: IER

0x60 - Interrupt Enable Register

idr1: IDR

0x64 - Interrupt Disable Register

imr1: IMR

0x68 - Interrupt Mask Register

isr1: ISR

0x6c - Interrupt Status Register

mar2: MAR

0x80 - Memory Address Register

psr2: PSR

0x84 - Peripheral Select Register

tcr2: TCR

0x88 - Transfer Counter Register

marr2: MARR

0x8c - Memory Address Reload Register

tcrr2: TCRR

0x90 - Transfer Counter Reload Register

cr2: CR

0x94 - Control Register

mr2: MR

0x98 - Mode Register

sr2: SR

0x9c - Status Register

ier2: IER

0xa0 - Interrupt Enable Register

idr2: IDR

0xa4 - Interrupt Disable Register

imr2: IMR

0xa8 - Interrupt Mask Register

isr2: ISR

0xac - Interrupt Status Register

mar3: MAR

0xc0 - Memory Address Register

psr3: PSR

0xc4 - Peripheral Select Register

tcr3: TCR

0xc8 - Transfer Counter Register

marr3: MARR

0xcc - Memory Address Reload Register

tcrr3: TCRR

0xd0 - Transfer Counter Reload Register

cr3: CR

0xd4 - Control Register

mr3: MR

0xd8 - Mode Register

sr3: SR

0xdc - Status Register

ier3: IER

0xe0 - Interrupt Enable Register

idr3: IDR

0xe4 - Interrupt Disable Register

imr3: IMR

0xe8 - Interrupt Mask Register

isr3: ISR

0xec - Interrupt Status Register

mar4: MAR

0x100 - Memory Address Register

psr4: PSR

0x104 - Peripheral Select Register

tcr4: TCR

0x108 - Transfer Counter Register

marr4: MARR

0x10c - Memory Address Reload Register

tcrr4: TCRR

0x110 - Transfer Counter Reload Register

cr4: CR

0x114 - Control Register

mr4: MR

0x118 - Mode Register

sr4: SR

0x11c - Status Register

ier4: IER

0x120 - Interrupt Enable Register

idr4: IDR

0x124 - Interrupt Disable Register

imr4: IMR

0x128 - Interrupt Mask Register

isr4: ISR

0x12c - Interrupt Status Register

mar5: MAR

0x140 - Memory Address Register

psr5: PSR

0x144 - Peripheral Select Register

tcr5: TCR

0x148 - Transfer Counter Register

marr5: MARR

0x14c - Memory Address Reload Register

tcrr5: TCRR

0x150 - Transfer Counter Reload Register

cr5: CR

0x154 - Control Register

mr5: MR

0x158 - Mode Register

sr5: SR

0x15c - Status Register

ier5: IER

0x160 - Interrupt Enable Register

idr5: IDR

0x164 - Interrupt Disable Register

imr5: IMR

0x168 - Interrupt Mask Register

isr5: ISR

0x16c - Interrupt Status Register

mar6: MAR

0x180 - Memory Address Register

psr6: PSR

0x184 - Peripheral Select Register

tcr6: TCR

0x188 - Transfer Counter Register

marr6: MARR

0x18c - Memory Address Reload Register

tcrr6: TCRR

0x190 - Transfer Counter Reload Register

cr6: CR

0x194 - Control Register

mr6: MR

0x198 - Mode Register

sr6: SR

0x19c - Status Register

ier6: IER

0x1a0 - Interrupt Enable Register

idr6: IDR

0x1a4 - Interrupt Disable Register

imr6: IMR

0x1a8 - Interrupt Mask Register

isr6: ISR

0x1ac - Interrupt Status Register

mar7: MAR

0x1c0 - Memory Address Register

psr7: PSR

0x1c4 - Peripheral Select Register

tcr7: TCR

0x1c8 - Transfer Counter Register

marr7: MARR

0x1cc - Memory Address Reload Register

tcrr7: TCRR

0x1d0 - Transfer Counter Reload Register

cr7: CR

0x1d4 - Control Register

mr7: MR

0x1d8 - Mode Register

sr7: SR

0x1dc - Status Register

ier7: IER

0x1e0 - Interrupt Enable Register

idr7: IDR

0x1e4 - Interrupt Disable Register

imr7: IMR

0x1e8 - Interrupt Mask Register

isr7: ISR

0x1ec - Interrupt Status Register

mar8: MAR

0x200 - Memory Address Register

psr8: PSR

0x204 - Peripheral Select Register

tcr8: TCR

0x208 - Transfer Counter Register

marr8: MARR

0x20c - Memory Address Reload Register

tcrr8: TCRR

0x210 - Transfer Counter Reload Register

cr8: CR

0x214 - Control Register

mr8: MR

0x218 - Mode Register

sr8: SR

0x21c - Status Register

ier8: IER

0x220 - Interrupt Enable Register

idr8: IDR

0x224 - Interrupt Disable Register

imr8: IMR

0x228 - Interrupt Mask Register

isr8: ISR

0x22c - Interrupt Status Register

mar9: MAR

0x240 - Memory Address Register

psr9: PSR

0x244 - Peripheral Select Register

tcr9: TCR

0x248 - Transfer Counter Register

marr9: MARR

0x24c - Memory Address Reload Register

tcrr9: TCRR

0x250 - Transfer Counter Reload Register

cr9: CR

0x254 - Control Register

mr9: MR

0x258 - Mode Register

sr9: SR

0x25c - Status Register

ier9: IER

0x260 - Interrupt Enable Register

idr9: IDR

0x264 - Interrupt Disable Register

imr9: IMR

0x268 - Interrupt Mask Register

isr9: ISR

0x26c - Interrupt Status Register

mar10: MAR

0x280 - Memory Address Register

psr10: PSR

0x284 - Peripheral Select Register

tcr10: TCR

0x288 - Transfer Counter Register

marr10: MARR

0x28c - Memory Address Reload Register

tcrr10: TCRR

0x290 - Transfer Counter Reload Register

cr10: CR

0x294 - Control Register

mr10: MR

0x298 - Mode Register

sr10: SR

0x29c - Status Register

ier10: IER

0x2a0 - Interrupt Enable Register

idr10: IDR

0x2a4 - Interrupt Disable Register

imr10: IMR

0x2a8 - Interrupt Mask Register

isr10: ISR

0x2ac - Interrupt Status Register

mar11: MAR

0x2c0 - Memory Address Register

psr11: PSR

0x2c4 - Peripheral Select Register

tcr11: TCR

0x2c8 - Transfer Counter Register

marr11: MARR

0x2cc - Memory Address Reload Register

tcrr11: TCRR

0x2d0 - Transfer Counter Reload Register

cr11: CR

0x2d4 - Control Register

mr11: MR

0x2d8 - Mode Register

sr11: SR

0x2dc - Status Register

ier11: IER

0x2e0 - Interrupt Enable Register

idr11: IDR

0x2e4 - Interrupt Disable Register

imr11: IMR

0x2e8 - Interrupt Mask Register

isr11: ISR

0x2ec - Interrupt Status Register

mar12: MAR

0x300 - Memory Address Register

psr12: PSR

0x304 - Peripheral Select Register

tcr12: TCR

0x308 - Transfer Counter Register

marr12: MARR

0x30c - Memory Address Reload Register

tcrr12: TCRR

0x310 - Transfer Counter Reload Register

cr12: CR

0x314 - Control Register

mr12: MR

0x318 - Mode Register

sr12: SR

0x31c - Status Register

ier12: IER

0x320 - Interrupt Enable Register

idr12: IDR

0x324 - Interrupt Disable Register

imr12: IMR

0x328 - Interrupt Mask Register

isr12: ISR

0x32c - Interrupt Status Register

mar13: MAR

0x340 - Memory Address Register

psr13: PSR

0x344 - Peripheral Select Register

tcr13: TCR

0x348 - Transfer Counter Register

marr13: MARR

0x34c - Memory Address Reload Register

tcrr13: TCRR

0x350 - Transfer Counter Reload Register

cr13: CR

0x354 - Control Register

mr13: MR

0x358 - Mode Register

sr13: SR

0x35c - Status Register

ier13: IER

0x360 - Interrupt Enable Register

idr13: IDR

0x364 - Interrupt Disable Register

imr13: IMR

0x368 - Interrupt Mask Register

isr13: ISR

0x36c - Interrupt Status Register

mar14: MAR

0x380 - Memory Address Register

psr14: PSR

0x384 - Peripheral Select Register

tcr14: TCR

0x388 - Transfer Counter Register

marr14: MARR

0x38c - Memory Address Reload Register

tcrr14: TCRR

0x390 - Transfer Counter Reload Register

cr14: CR

0x394 - Control Register

mr14: MR

0x398 - Mode Register

sr14: SR

0x39c - Status Register

ier14: IER

0x3a0 - Interrupt Enable Register

idr14: IDR

0x3a4 - Interrupt Disable Register

imr14: IMR

0x3a8 - Interrupt Mask Register

isr14: ISR

0x3ac - Interrupt Status Register

mar15: MAR

0x3c0 - Memory Address Register

psr15: PSR

0x3c4 - Peripheral Select Register

tcr15: TCR

0x3c8 - Transfer Counter Register

marr15: MARR

0x3cc - Memory Address Reload Register

tcrr15: TCRR

0x3d0 - Transfer Counter Reload Register

cr15: CR

0x3d4 - Control Register

mr15: MR

0x3d8 - Mode Register

sr15: SR

0x3dc - Status Register

ier15: IER

0x3e0 - Interrupt Enable Register

idr15: IDR

0x3e4 - Interrupt Disable Register

imr15: IMR

0x3e8 - Interrupt Mask Register

isr15: ISR

0x3ec - Interrupt Status Register

pcontrol: PCONTROL

0x800 - Performance Control Register

prdata0: PRDATA0

0x804 - Channel 0 Read Data Cycles

prstall0: PRSTALL0

0x808 - Channel 0 Read Stall Cycles

prlat0: PRLAT0

0x80c - Channel 0 Read Max Latency

pwdata0: PWDATA0

0x810 - Channel 0 Write Data Cycles

pwstall0: PWSTALL0

0x814 - Channel 0 Write Stall Cycles

pwlat0: PWLAT0

0x818 - Channel0 Write Max Latency

prdata1: PRDATA1

0x81c - Channel 1 Read Data Cycles

prstall1: PRSTALL1

0x820 - Channel Read Stall Cycles

prlat1: PRLAT1

0x824 - Channel 1 Read Max Latency

pwdata1: PWDATA1

0x828 - Channel 1 Write Data Cycles

pwstall1: PWSTALL1

0x82c - Channel 1 Write stall Cycles

pwlat1: PWLAT1

0x830 - Channel 1 Read Max Latency

version: VERSION

0x834 - Version Register

Trait Implementations