Type Definition atsam4lc2a_pac::twis0::cr::W

type W = W<u32, CR>;

Writer for register CR

Implementations

impl W

pub fn sen(&mut self) -> SEN_W<'_>

Bit 0 - Slave Enable

pub fn smen(&mut self) -> SMEN_W<'_>

Bit 1 - SMBus Mode Enable

pub fn smatch(&mut self) -> SMATCH_W<'_>

Bit 2 - Slave Address Match

pub fn gcmatch(&mut self) -> GCMATCH_W<'_>

Bit 3 - General Call Address Match

pub fn stren(&mut self) -> STREN_W<'_>

Bit 4 - Clock Stretch Enable

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 7 - Software Reset

pub fn smbalert(&mut self) -> SMBALERT_W<'_>

Bit 8 - SMBus Alert

pub fn smda(&mut self) -> SMDA_W<'_>

Bit 9 - SMBus Default Address

pub fn smhh(&mut self) -> SMHH_W<'_>

Bit 10 - SMBus Host Header

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 11 - Packet Error Checking Enable

pub fn ack(&mut self) -> ACK_W<'_>

Bit 12 - Slave Receiver Data Phase ACK Value

pub fn cup(&mut self) -> CUP_W<'_>

Bit 13 - NBYTES Count Up

pub fn soam(&mut self) -> SOAM_W<'_>

Bit 14 - Stretch Clock on Address Match

pub fn sodr(&mut self) -> SODR_W<'_>

Bit 15 - Stretch Clock on Data Byte Reception

pub fn adr(&mut self) -> ADR_W<'_>

Bits 16:25 - Slave Address

pub fn tenbit(&mut self) -> TENBIT_W<'_>

Bit 26 - Ten Bit Address Match

pub fn bridge(&mut self) -> BRIDGE_W<'_>

Bit 27 - Bridge Control Enable