Type Definition ambiq_apollo3p_pac::bleif::bstatus::R

type R = R<u32, BSTATUS>;

Reader of register BSTATUS

Methods

impl R

pub fn blehreq(&self) -> BLEHREQ_R

Bit 12 - Value of the BLEHREQ signal to the power control unit. The BLEHREQ signal is sent from the BLEIF module to the power control module to request the BLEH power up. When the BLEHACK signal is asserted, BLEH power is stable and ready for use.

pub fn blehack(&self) -> BLEHACK_R

Bit 11 - Value of the BLEHACK signal from the power control unit. If the signal is '1', the BLEH power is active and ready for use.

pub fn pwrst(&self) -> PWRST_R

Bits 8:10 - Current status of the power state machine

pub fn bleirq(&self) -> BLEIRQ_R

Bit 7 - Status of the BLEIRQ signal from the BLE Core. A value of 1 indicates that read data is available in the core and a read operation needs to be performed.

pub fn wakeup(&self) -> WAKEUP_R

Bit 6 - Value of the WAKEUP signal to the BLE Core . The WAKEUP signals is sent from the BLEIF to the BLECORE to request the BLE Core transition from sleep state to active state.

pub fn dcdcflag(&self) -> DCDCFLAG_R

Bit 5 - Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG is a signal to the BLE Core indicating that the BLEH power is active.

pub fn dcdcreq(&self) -> DCDCREQ_R

Bit 4 - Value of the DCDCREQ signal from the BLE Core. The DCDCREQ signal is sent from the core to the BLEIF module when the BLE core requires BLEH power to be active. When activated, this is indicated by DCDCFLAG going to 1.

pub fn spistatus(&self) -> SPISTATUS_R

Bit 3 - Value of the SPISTATUS signal from the BLE Core. The signal is asserted when the BLE Core is able to accept write data via the SPI interface. Data should be transmitted to the BLE core only when this signal is 1. The hardware will automatically wait for this signal prior to performing a write operation if flow control is active.

pub fn b2mstate(&self) -> B2MSTATE_R

Bits 0:2 - State of the BLE Core logic.