[−][src]Struct ambiq_apollo3_pac::mcuctrl::RegisterBlock

#[repr(C)]

pub struct RegisterBlock {
    pub chippn: CHIPPN,
    pub chipid0: CHIPID0,
    pub chipid1: CHIPID1,
    pub chiprev: CHIPREV,
    pub vendorid: VENDORID,
    pub sku: SKU,
    pub featureenable: FEATUREENABLE,
    pub debugger: DEBUGGER,
    pub bodctrl: BODCTRL,
    pub adcpwrdly: ADCPWRDLY,
    pub adccal: ADCCAL,
    pub adcbattload: ADCBATTLOAD,
    pub adctrim: ADCTRIM,
    pub adcrefcomp: ADCREFCOMP,
    pub xtalctrl: XTALCTRL,
    pub xtalgenctrl: XTALGENCTRL,
    pub miscctrl: MISCCTRL,
    pub bootloader: BOOTLOADER,
    pub shadowvalid: SHADOWVALID,
    pub scratch0: SCRATCH0,
    pub scratch1: SCRATCH1,
    pub icodefaultaddr: ICODEFAULTADDR,
    pub dcodefaultaddr: DCODEFAULTADDR,
    pub sysfaultaddr: SYSFAULTADDR,
    pub faultstatus: FAULTSTATUS,
    pub faultcaptureen: FAULTCAPTUREEN,
    pub dbgr1: DBGR1,
    pub dbgr2: DBGR2,
    pub pmuenable: PMUENABLE,
    pub tpiuctrl: TPIUCTRL,
    pub otapointer: OTAPOINTER,
    pub apbdmactrl: APBDMACTRL,
    pub srammode: SRAMMODE,
    pub kextclksel: KEXTCLKSEL,
    pub simobuck4: SIMOBUCK4,
    pub blebuck2: BLEBUCK2,
    pub flashwprot0: FLASHWPROT0,
    pub flashwprot1: FLASHWPROT1,
    pub flashrprot0: FLASHRPROT0,
    pub flashrprot1: FLASHRPROT1,
    pub dmasramwriteprotect0: DMASRAMWRITEPROTECT0,
    pub dmasramwriteprotect1: DMASRAMWRITEPROTECT1,
    pub dmasramreadprotect0: DMASRAMREADPROTECT0,
    pub dmasramreadprotect1: DMASRAMREADPROTECT1,
    // some fields omitted
}

Register block

Fields

chippn: CHIPPN

0x00 - Chip Information Register

chipid0: CHIPID0

0x04 - Unique Chip ID 0

chipid1: CHIPID1

0x08 - Unique Chip ID 1

chiprev: CHIPREV

0x0c - Chip Revision

vendorid: VENDORID

0x10 - Unique Vendor ID

sku: SKU

0x14 - Unique Chip SKU

featureenable: FEATUREENABLE

0x18 - Feature Enable on Burst and BLE

debugger: DEBUGGER

0x20 - Debugger Control

bodctrl: BODCTRL

0x100 - BOD control Register

adcpwrdly: ADCPWRDLY

0x104 - ADC Power Up Delay Control

adccal: ADCCAL

0x10c - ADC Calibration Control

adcbattload: ADCBATTLOAD

0x110 - ADC Battery Load Enable

adctrim: ADCTRIM

0x118 - ADC Trims

adcrefcomp: ADCREFCOMP

0x11c - ADC Referece Keeper and Comparator Control

xtalctrl: XTALCTRL

0x120 - XTAL Oscillator Control

xtalgenctrl: XTALGENCTRL

0x124 - XTAL Oscillator General Control

miscctrl: MISCCTRL

0x198 - Miscellaneous control register.

bootloader: BOOTLOADER

0x1a0 - Bootloader and secure boot functions

shadowvalid: SHADOWVALID

0x1a4 - Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.

scratch0: SCRATCH0

0x1b0 - Scratch register that is not reset by any reset

scratch1: SCRATCH1

0x1b4 - Scratch register that is not reset by any reset

icodefaultaddr: ICODEFAULTADDR

0x1c0 - ICODE bus address which was present when a bus fault occurred.

dcodefaultaddr: DCODEFAULTADDR

0x1c4 - DCODE bus address which was present when a bus fault occurred.

sysfaultaddr: SYSFAULTADDR

0x1c8 - System bus address which was present when a bus fault occurred.

faultstatus: FAULTSTATUS

0x1cc - Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.

faultcaptureen: FAULTCAPTUREEN

0x1d0 - Enable the fault capture registers

dbgr1: DBGR1

0x200 - Read-only debug register 1

dbgr2: DBGR2

0x204 - Read-only debug register 2

pmuenable: PMUENABLE

0x220 - Control bit to enable/disable the PMU

tpiuctrl: TPIUCTRL

0x250 - TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.

otapointer: OTAPOINTER

0x264 - OTA (Over the Air) Update Pointer/Status. Reset only by POA

apbdmactrl: APBDMACTRL

0x280 - DMA Control Register. Determines misc settings for DMA operation

srammode: SRAMMODE

0x284 - SRAM Controller mode bits

kextclksel: KEXTCLKSEL

0x348 - Key Register to enable the use of external clock selects via the EXTCLKSEL reg

simobuck4: SIMOBUCK4

0x35c - SIMO Buck Control Reg1

blebuck2: BLEBUCK2

0x368 - BLEBUCK2 Control Reg

flashwprot0: FLASHWPROT0

0x3a0 - Flash Write Protection Bits

flashwprot1: FLASHWPROT1

0x3a4 - Flash Write Protection Bits

flashrprot0: FLASHRPROT0

0x3b0 - Flash Read Protection Bits

flashrprot1: FLASHRPROT1

0x3b4 - Flash Read Protection Bits

dmasramwriteprotect0: DMASRAMWRITEPROTECT0

0x3c0 - SRAM write-protection bits.

dmasramwriteprotect1: DMASRAMWRITEPROTECT1

0x3c4 - SRAM write-protection bits.

dmasramreadprotect0: DMASRAMREADPROTECT0

0x3d0 - SRAM read-protection bits.

dmasramreadprotect1: DMASRAMREADPROTECT1

0x3d4 - SRAM read-protection bits.

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