[−][src]Module ambiq_apollo1_pac::mcuctrl

MCU Miscellaneous Control Logic

Modules

bandgapen	Band Gap Enable
chip_info	Chip Information Register
chipid0	Unique Chip ID 0
chipid1	Unique Chip ID 1
chiprev	Chip Revision
dcodefaultaddr	DCODE bus address which was present when a bus fault occurred.
faultcaptureen	Enable the fault capture registers
faultstatus	Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.
flashpwrdis	Disables individual banks of the Flash array
icodefaultaddr	ICODE bus address which was present when a bus fault occurred.
srampwdinsleep	Powerdown an SRAM Bank in Deep Sleep mode
srampwrdis	Disables individual banks of the SRAM array
supplysrc	Memory and Core Voltage Supply Source Select Register
supplystatus	Memory and Core Voltage Supply Source Status Register
sysfaultaddr	System bus address which was present when a bus fault occurred.
tpiuctrl	TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.

Register block

BANDGAPEN	Band Gap Enable
CHIPID0	Unique Chip ID 0
CHIPID1	Unique Chip ID 1
CHIPREV	Chip Revision
CHIP_INFO	Chip Information Register
DCODEFAULTADDR	DCODE bus address which was present when a bus fault occurred.
FAULTCAPTUREEN	Enable the fault capture registers
FAULTSTATUS	Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.
FLASHPWRDIS	Disables individual banks of the Flash array
ICODEFAULTADDR	ICODE bus address which was present when a bus fault occurred.
SRAMPWDINSLEEP	Powerdown an SRAM Bank in Deep Sleep mode
SRAMPWRDIS	Disables individual banks of the SRAM array
SUPPLYSRC	Memory and Core Voltage Supply Source Select Register
SUPPLYSTATUS	Memory and Core Voltage Supply Source Status Register
SYSFAULTADDR	System bus address which was present when a bus fault occurred.
TPIUCTRL	TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.