Enum adf4351::register::Pr1Prescaler

pub enum Pr1Prescaler {
    Pr45,
    Pr89,
}

The dual-modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD values, determines the overall division ratio from the VCO output to the PFD input. The PR1 bit (DB27) in Register 1 sets the prescaler value. Operating at CML levels, the prescaler takes the clock from the VCO output and divides it down for the counters. The prescaler is based on a synchronous 4/5 core. When the prescaler is set to 4/5, the maximum RF frequency allowed is 3.6 GHz. Therefore, when operating the ADF4351 above 3.6 GHz, the prescaler must be set to 8/9.

Variants

Pr45

Prescaler = 4/5: INT N MIN = 23

Pr89

Prescaler = 8/9: INT N MIN = 75

Trait Implementations

impl BitField<R1> for Pr1Prescaler

fn num_bits() -> u8

Number of bits in the bit field

fn offset() -> u8

Offset from 0

fn mask() -> u32

impl Clone for Pr1Prescaler

fn clone(&self) -> Pr1Prescaler

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for Pr1Prescaler

impl Debug for Pr1Prescaler

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<u32> for Pr1Prescaler

fn from(x: u32) -> Self

Performs the conversion.

impl Into<u32> for Pr1Prescaler

fn into(self) -> u32

Performs the conversion.