Enum adf4351::register::CycleSlipReduction

pub enum CycleSlipReduction {
    Disabled,
    Enabled,
}

Setting the DB18 bit to 1 enables cycle slip reduction. CSR is a method for improving lock times. Note that the signal at the phase frequency detector (PFD) must have a 50% duty cycle for cycle slip reduction to work. The charge pump current setting must also be set to a minimum. For more information, see the Cycle Slip Reduction for Faster Lock Times section.

Variants

Disabled

Enabled

Trait Implementations

impl BitField<R3> for CycleSlipReduction

fn num_bits() -> u8

Number of bits in the bit field

fn offset() -> u8

Offset from 0

fn mask() -> u32

impl Clone for CycleSlipReduction

fn clone(&self) -> CycleSlipReduction

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for CycleSlipReduction

impl Debug for CycleSlipReduction

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<u32> for CycleSlipReduction

fn from(x: u32) -> Self

Performs the conversion.

impl Into<u32> for CycleSlipReduction

fn into(self) -> u32

Performs the conversion.