Enum adf4351::register::ClockDividerMode

pub enum ClockDividerMode {
    Off,
    FastLock,
    Resync,
}

Bits[DB16:DB15] must be set to 10 to activate phase resync (see the Phase Resync section). These bits must be set to 01 to activate fast lock (see the Fast Lock Timer and Register Sequences section). Setting Bits[DB16:DB15] to 00 disables the clock divider (see Figure 27).

Variants

Off

FastLock

Resync

Trait Implementations

impl BitField<R3> for ClockDividerMode

fn num_bits() -> u8

Number of bits in the bit field

fn offset() -> u8

Offset from 0

fn mask() -> u32

impl Clone for ClockDividerMode

fn clone(&self) -> ClockDividerMode

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for ClockDividerMode

impl Debug for ClockDividerMode

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<u32> for ClockDividerMode

fn from(x: u32) -> Self

Performs the conversion.

impl Into<u32> for ClockDividerMode

fn into(self) -> u32

Performs the conversion.