Alignment check enable. This is the enable bit for Alignment fault checking at EL1 and EL0.
Cacheability control, for data accesses.
Traps EL0 execution of DC ZVA instructions to EL1, from AArch64 state only.
Endianness of data accesses at EL0.
Endianness of data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime.
Instruction access Cacheability control, for accesses at EL0 and
EL1:
MMU enable for EL1 and EL0 stage 1 address translation. Possible values of this bit are:
Non-aligned access. This bit controls generation of Alignment faults at EL1 and EL0 under certain conditions.
Traps EL0 execution of WFE instructions to EL1, from both Execution states.
Traps EL0 executions of WFI instructions to EL1, from both execution states:
SP Alignment check enable.
SP Alignment check enable for EL0.
Traps EL0 execution of cache maintenance instructions to EL1, from AArch64 state only.
Traps EL0 accesses to the CTR_EL0 to EL1, from AArch64 state only.
User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the
PSTATE.{D, A, I, F} masks to EL1, from AArch64 state only.
Write permission implies XN (Execute-never). For the EL1&0 translation regime, this bit can force
all memory regions that are writable to be treated as XN.