#[repr(u64)]pub enum Value {
TrapEl0El1 = 0,
TrapEl0 = 1,
TrapEl1El0 = 2,
TrapNothing = 3,
}
Expand description
Traps execution at EL0 and EL1 of instructions that access the Advanced SIMD and floating-point registers from both Execution states to EL1, reported using ESR_ELx.EC value 0x07, or to EL2 reported using ESR_ELx.EC value 0x00 when EL2 is implemented and enabled in the current Security state and HCR_EL2.TGE is 1, as follows:
-
In AArch64 state, accesses to FPCR, FPSR, any of the SIMD and floating-point registers V0-V31, including their views as D0-31 registers or S0-31 registers.
-
In AArch32 state, FPSCR, and any of the SIMD and floating-point registers Q0-15, including their views as D0-31 registers or S0-31 registers.
Traps execution at EL1 and EL0 of SVE instructions to EL1, or to EL2 when El2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1. The exception is reported using ESR_ELx.EC value 0x07.
A trap taken as a result of [CPACR_EL1::ZEN
] has precendence over a trap taken
as a result of [CPACR_EL1::FPEN
].
On a Warm reset, this fields resets to an undefined value.
Variants§
TrapEl0El1 = 0
This control causes execution of these instructions at EL0 and EL1 to be trapped.
TrapEl0 = 1
This control causes execution of these instructions at EL0 to be trapped, but does not cause any instructions at EL1 to be trapped.
TrapEl1El0 = 2
This control causes execution of these instructions at EL1 and EL0 to be trapped.
TrapNothing = 3
This control does not cause execution of any instructions to be trapped.