[−][src]Struct ADuCM302x::sport0::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub ctl_a: CTL_A,
    pub div_a: DIV_A,
    pub ien_a: IEN_A,
    pub stat_a: STAT_A,
    pub numtran_a: NUMTRAN_A,
    pub cnvt_a: CNVT_A,
    pub tx_a: TX_A,
    pub rx_a: RX_A,
    pub ctl_b: CTL_B,
    pub div_b: DIV_B,
    pub ien_b: IEN_B,
    pub stat_b: STAT_B,
    pub numtran_b: NUMTRAN_B,
    pub cnvt_b: CNVT_B,
    pub tx_b: TX_B,
    pub rx_b: RX_B,
    // some fields omitted
}

Register block

Fields

ctl_a: CTL_A

0x00 - Half SPORT 'A' Control

div_a: DIV_A

0x04 - Half SPORT 'A' Divisor

ien_a: IEN_A

0x08 - Half SPORT A's Interrupt Enable

stat_a: STAT_A

0x0c - Half SPORT A's Status

numtran_a: NUMTRAN_A

0x10 - Half SPORT A Number of Transfers

cnvt_a: CNVT_A

0x14 - Half SPORT 'A' CNV Width

tx_a: TX_A

0x20 - Half SPORT 'A' Tx Buffer

rx_a: RX_A

0x28 - Half SPORT 'A' Rx Buffer

ctl_b: CTL_B

0x40 - Half SPORT 'B' Control

div_b: DIV_B

0x44 - Half SPORT 'B' Divisor

ien_b: IEN_B

0x48 - Half SPORT B's Interrupt Enable

stat_b: STAT_B

0x4c - Half SPORT B's Status

numtran_b: NUMTRAN_B

0x50 - Half SPORT B Number of Transfers

cnvt_b: CNVT_B

0x54 - Half SPORT 'B' CNV Width

tx_b: TX_B

0x60 - Half SPORT 'B' Tx Buffer

rx_b: RX_B

0x68 - Half SPORT 'B' Rx Buffer

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