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Crate cortex_m

Crate cortex_m 

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Expand description

Low level access to Cortex-M processors

This crate provides:

  • Access to core peripherals like NVIC, SCB and SysTick.
  • Access to core registers like CONTROL, MSP and PSR.
  • Interrupt manipulation mechanisms
  • Safe wrappers around Cortex-M specific instructions like bkpt

§Optional features

§critical-section-single-core

This feature enables a critical-section implementation suitable for single-core targets, based on disabling interrupts globally.

It is unsound to enable it on multi-core targets or for code running in unprivileged mode, and may cause functional problems in systems where some interrupts must not be disabled or critical sections are managed as part of an RTOS. In these cases, you should use a target-specific implementation instead, typically provided by a HAL or RTOS crate.

The critical section has been optimized to block interrupts for as few cycles as possible, but – due to critical-section implementation details – incurs branches in a normal build configuration. For minimal interrupt latency, you can achieve inlining by enabling linker-plugin-based LTO.

§cm7-r0p1

This feature enables workarounds for errata found on Cortex-M7 chips with revision r0p1. Some functions in this crate only work correctly on those chips if this Cargo feature is enabled (the functions are documented accordingly).

§linker-plugin-lto

This feature links against prebuilt assembly blobs that are compatible with Linker-Plugin LTO. This allows inlining assembly routines into the caller, and works on stable Rust (but note the drawbacks below!).

If you want to use this feature, you need to be aware of a few things:

  • You need to make sure that -Clinker-plugin-lto is passed to rustc. Please refer to the Linker-Plugin LTO documentation for details.

  • You have to use a Rust version whose LLVM version is compatible with the toolchain in asm-toolchain.

  • Due to a Rust bug in compiler versions before 1.49, this option does not work with optimization levels s and z.

§secure-mode

Adds extra non-secure peripherals to the Peripherals struct. Only set when your processor is running in Secure mode, and you need to control operations in nonsecure mode (e.g. to bootload some nonsecure firmware).

§inline-asm

This feature is deprecated. Enabling this feature does nothing - it exists for backwards-compatibility only. It will be removed in a future version of this crate.

§Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.85 and up. It might compile with older versions but that may change in any new patch release.

Re-exports§

pub use crate::peripheral::Peripherals;

Modules§

asm
Miscellaneous assembly instructions
delay
A delay driver based on SysTick.
interrupt
Interrupts
peripheral
Core peripherals.
prelude
Prelude
psp
Process Stack Pointer support
register
Processor core registers

Macros§

iprint
Macro for sending a formatted string through an ITM channel
iprintln
Macro for sending a formatted string through an ITM channel, with a newline.
singleton
Macro to create a mutable reference to a statically allocated value