cortex_m/register/
faultmask.rs

1//! Fault Mask Register
2
3#[cfg(cortex_m)]
4use core::arch::asm;
5use cortex_m_macros::asm_cfg;
6
7/// All exceptions are ...
8#[derive(Clone, Copy, Debug, Eq, PartialEq)]
9pub enum Faultmask {
10    /// Active
11    Active,
12    /// Inactive, expect for NMI
13    Inactive,
14}
15
16impl Faultmask {
17    /// All exceptions are active
18    #[inline]
19    pub fn is_active(self) -> bool {
20        self == Faultmask::Active
21    }
22
23    /// All exceptions, except for NMI, are inactive
24    #[inline]
25    pub fn is_inactive(self) -> bool {
26        self == Faultmask::Inactive
27    }
28}
29
30/// Reads the CPU register
31#[inline]
32#[asm_cfg(any(armv7m, armv8m_main))]
33pub fn read() -> Faultmask {
34    let r: u32;
35    unsafe { asm!("mrs {}, FAULTMASK", out(reg) r, options(nomem, nostack, preserves_flags)) };
36    if r & (1 << 0) == (1 << 0) {
37        Faultmask::Inactive
38    } else {
39        Faultmask::Active
40    }
41}
cortex_m/register/faultmask.rs

cortex_m/register/
faultmask.rs
