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cortex_m/register/
basepri_max.rs

1//! Base Priority Mask Register (conditional write)
2
3#[cfg(any(armv7m, armv8m))]
4use core::arch::asm;
5use cortex_m_macros::asm_cfg;
6
7/// Writes to BASEPRI *if*
8///
9/// - `basepri != 0` AND `basepri::read() == 0`, OR
10/// - `basepri != 0` AND `basepri < basepri::read()`
11///
12/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
13/// `cm7-r0p1` Cargo feature or this function WILL misbehave.
14#[inline]
15#[asm_cfg(any(armv7m, armv8m_main))]
16pub fn write(basepri: u8) {
17    #[cfg(not(feature = "cm7-r0p1"))]
18    {
19        unsafe {
20            asm!("msr BASEPRI_MAX, {}", in(reg) basepri, options(nomem, nostack, preserves_flags))
21        };
22    }
23
24    #[cfg(feature = "cm7-r0p1")]
25    {
26        unsafe {
27            asm!(
28                "mrs {1}, PRIMASK",
29                "cpsid i",
30                "tst.w {1}, #1",
31                "msr BASEPRI_MAX, {0}",
32                "it ne",
33                "bxne lr",
34                "cpsie i",
35                in(reg) basepri,
36                out(reg) _,
37                options(nomem, nostack, preserves_flags),
38            )
39        };
40    }
41}