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cortex_m/register/
basepri.rs

1//! Base Priority Mask Register
2
3#[cfg(any(armv7m, armv8m))]
4use core::arch::asm;
5use cortex_m_macros::asm_cfg;
6
7/// Reads the CPU register
8#[inline]
9#[asm_cfg(any(armv7m, armv8m_main))]
10pub fn read() -> u8 {
11    let r;
12    unsafe { asm!("mrs {}, BASEPRI", out(reg) r, options(nomem, nostack, preserves_flags)) };
13    r
14}
15
16/// Writes to the CPU register
17///
18/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
19/// `cm7-r0p1` Cargo feature or this function WILL misbehave.
20#[inline]
21#[asm_cfg(any(armv7m, armv8m_main))]
22pub unsafe fn write(basepri: u8) {
23    #[cfg(not(feature = "cm7-r0p1"))]
24    {
25        unsafe {
26            asm!("msr BASEPRI, {}", in(reg) basepri, options(nomem, nostack, preserves_flags))
27        };
28    }
29
30    #[cfg(feature = "cm7-r0p1")]
31    {
32        unsafe {
33            asm!(
34                "mrs {1}, PRIMASK",
35                "cpsid i",
36                "tst.w {1}, #1",
37                "msr BASEPRI, {0}",
38                "it ne",
39                "bxne lr",
40                "cpsie i",
41                in(reg) basepri,
42                out(reg) _,
43                options(nomem, nostack, preserves_flags),
44            )
45        };
46    }
47}