cortex_m/register/
apsr.rs1#[cfg(cortex_m)]
4use core::arch::asm;
5use cortex_m_macros::asm_cfg;
6
7#[derive(Clone, Copy, Debug)]
9pub struct Apsr {
10 bits: u32,
11}
12
13impl Apsr {
14 #[inline]
16 pub fn bits(self) -> u32 {
17 self.bits
18 }
19
20 #[inline]
22 pub fn q(self) -> bool {
23 self.bits & (1 << 27) == (1 << 27)
24 }
25
26 #[inline]
28 pub fn v(self) -> bool {
29 self.bits & (1 << 28) == (1 << 28)
30 }
31
32 #[inline]
34 pub fn c(self) -> bool {
35 self.bits & (1 << 29) == (1 << 29)
36 }
37
38 #[inline]
40 pub fn z(self) -> bool {
41 self.bits & (1 << 30) == (1 << 30)
42 }
43
44 #[inline]
46 pub fn n(self) -> bool {
47 self.bits & (1 << 31) == (1 << 31)
48 }
49}
50
51#[inline]
53#[asm_cfg(cortex_m)]
54pub fn read() -> Apsr {
55 let bits;
56 unsafe { asm!("mrs {}, APSR", out(reg) bits, options(nomem, nostack, preserves_flags)) };
57 Apsr { bits }
58}