cortex_m/peripheral/
dwt.rs

1//! Data Watchpoint and Trace unit
2
3#[cfg(not(armv6m))]
4use volatile_register::WO;
5use volatile_register::{RO, RW};
6
7use crate::peripheral::DWT;
8
9/// Register block
10#[repr(C)]
11pub struct RegisterBlock {
12    /// Control
13    pub ctrl: RW<u32>,
14    /// Cycle Count
15    #[cfg(not(armv6m))]
16    pub cyccnt: RW<u32>,
17    /// CPI Count
18    #[cfg(not(armv6m))]
19    pub cpicnt: RW<u32>,
20    /// Exception Overhead Count
21    #[cfg(not(armv6m))]
22    pub exccnt: RW<u32>,
23    /// Sleep Count
24    #[cfg(not(armv6m))]
25    pub sleepcnt: RW<u32>,
26    /// LSU Count
27    #[cfg(not(armv6m))]
28    pub lsucnt: RW<u32>,
29    /// Folded-instruction Count
30    #[cfg(not(armv6m))]
31    pub foldcnt: RW<u32>,
32    /// Cortex-M0(+) does not have  these parts
33    #[cfg(armv6m)]
34    reserved: [u32; 6],
35    /// Program Counter Sample
36    pub pcsr: RO<u32>,
37    /// Comparators
38    #[cfg(armv6m)]
39    pub c: [Comparator; 2],
40    #[cfg(not(armv6m))]
41    /// Comparators
42    pub c: [Comparator; 16],
43    #[cfg(not(armv6m))]
44    reserved: [u32; 932],
45    /// Lock Access
46    #[cfg(not(armv6m))]
47    pub lar: WO<u32>,
48    /// Lock Status
49    #[cfg(not(armv6m))]
50    pub lsr: RO<u32>,
51}
52
53/// Comparator
54#[repr(C)]
55pub struct Comparator {
56    /// Comparator
57    pub comp: RW<u32>,
58    /// Comparator Mask
59    pub mask: RW<u32>,
60    /// Comparator Function
61    pub function: RW<u32>,
62    reserved: u32,
63}
64
65// DWT CTRL register fields
66const NUMCOMP_OFFSET: u32 = 28;
67#[cfg(not(armv6m))]
68const NOTRCPKT: u32 = 1 << 27;
69#[cfg(not(armv6m))]
70const NOEXTTRIG: u32 = 1 << 26;
71#[cfg(not(armv6m))]
72const NOCYCCNT: u32 = 1 << 25;
73#[cfg(not(armv6m))]
74const NOPRFCNT: u32 = 1 << 24;
75#[cfg(not(armv6m))]
76const CYCCNTENA: u32 = 1 << 0;
77
78impl DWT {
79    /// Number of comparators implemented
80    ///
81    /// A value of zero indicates no comparator support.
82    #[inline]
83    pub fn num_comp() -> u8 {
84        // NOTE(unsafe) atomic read with no side effects
85        unsafe { ((*Self::PTR).ctrl.read() >> NUMCOMP_OFFSET) as u8 }
86    }
87
88    /// Returns `true` if the the implementation supports sampling and exception tracing
89    #[cfg(not(armv6m))]
90    #[inline]
91    pub fn has_exception_trace() -> bool {
92        // NOTE(unsafe) atomic read with no side effects
93        unsafe { (*Self::PTR).ctrl.read() & NOTRCPKT == 0 }
94    }
95
96    /// Returns `true` if the implementation includes external match signals
97    #[cfg(not(armv6m))]
98    #[inline]
99    pub fn has_external_match() -> bool {
100        // NOTE(unsafe) atomic read with no side effects
101        unsafe { (*Self::PTR).ctrl.read() & NOEXTTRIG == 0 }
102    }
103
104    /// Returns `true` if the implementation supports a cycle counter
105    #[cfg(not(armv6m))]
106    #[inline]
107    pub fn has_cycle_counter() -> bool {
108        // NOTE(unsafe) atomic read with no side effects
109        unsafe { (*Self::PTR).ctrl.read() & NOCYCCNT == 0 }
110    }
111
112    /// Returns `true` if the implementation the profiling counters
113    #[cfg(not(armv6m))]
114    #[inline]
115    pub fn has_profiling_counter() -> bool {
116        // NOTE(unsafe) atomic read with no side effects
117        unsafe { (*Self::PTR).ctrl.read() & NOPRFCNT == 0 }
118    }
119
120    /// Enables the cycle counter
121    ///
122    /// The global trace enable ([`DCB::enable_trace`]) should be set before
123    /// enabling the cycle counter, the processor may ignore writes to the
124    /// cycle counter enable if the global trace is disabled
125    /// (implementation defined behaviour).
126    ///
127    /// [`DCB::enable_trace`]: crate::peripheral::DCB::enable_trace
128    #[cfg(not(armv6m))]
129    #[inline]
130    pub fn enable_cycle_counter(&mut self) {
131        unsafe { self.ctrl.modify(|r| r | CYCCNTENA) }
132    }
133
134    /// Disables the cycle counter
135    #[cfg(not(armv6m))]
136    #[inline]
137    pub fn disable_cycle_counter(&mut self) {
138        unsafe { self.ctrl.modify(|r| r & !CYCCNTENA) }
139    }
140
141    /// Returns `true` if the cycle counter is enabled
142    #[cfg(not(armv6m))]
143    #[inline]
144    pub fn cycle_counter_enabled() -> bool {
145        // NOTE(unsafe) atomic read with no side effects
146        unsafe { (*Self::PTR).ctrl.read() & CYCCNTENA != 0 }
147    }
148
149    /// Returns the current clock cycle count
150    #[cfg(not(armv6m))]
151    #[inline]
152    #[deprecated(
153        since = "0.7.4",
154        note = "Use `cycle_count` which follows the C-GETTER convention"
155    )]
156    pub fn get_cycle_count() -> u32 {
157        Self::cycle_count()
158    }
159
160    /// Returns the current clock cycle count
161    #[cfg(not(armv6m))]
162    #[inline]
163    pub fn cycle_count() -> u32 {
164        // NOTE(unsafe) atomic read with no side effects
165        unsafe { (*Self::PTR).cyccnt.read() }
166    }
167
168    /// Set the cycle count
169    #[cfg(not(armv6m))]
170    #[inline]
171    pub fn set_cycle_count(&mut self, count: u32) {
172        unsafe { self.cyccnt.write(count) }
173    }
174
175    /// Removes the software lock on the DWT
176    ///
177    /// Some devices, like the STM32F7, software lock the DWT after a power cycle.
178    #[cfg(not(armv6m))]
179    #[inline]
180    pub fn unlock() {
181        // NOTE(unsafe) atomic write to a stateless, write-only register
182        unsafe { (*Self::PTR).lar.write(0xC5AC_CE55) }
183    }
184
185    /// Get the CPI count
186    ///
187    /// Counts additional cycles required to execute multi-cycle instructions,
188    /// except those recorded by [`lsu_count`], and counts any instruction fetch
189    /// stalls.
190    ///
191    /// [`lsu_count`]: DWT::lsu_count
192    #[cfg(not(armv6m))]
193    #[inline]
194    pub fn cpi_count() -> u8 {
195        // NOTE(unsafe) atomic read with no side effects
196        unsafe { (*Self::PTR).cpicnt.read() as u8 }
197    }
198
199    /// Set the CPI count
200    #[cfg(not(armv6m))]
201    #[inline]
202    pub fn set_cpi_count(&mut self, count: u8) {
203        unsafe { self.cpicnt.write(count as u32) }
204    }
205
206    /// Get the total cycles spent in exception processing
207    #[cfg(not(armv6m))]
208    #[inline]
209    pub fn exception_count() -> u8 {
210        // NOTE(unsafe) atomic read with no side effects
211        unsafe { (*Self::PTR).exccnt.read() as u8 }
212    }
213
214    /// Set the exception count
215    #[cfg(not(armv6m))]
216    #[inline]
217    pub fn set_exception_count(&mut self, count: u8) {
218        unsafe { self.exccnt.write(count as u32) }
219    }
220
221    /// Get the total number of cycles that the processor is sleeping
222    ///
223    /// ARM recommends that this counter counts all cycles when the processor is sleeping,
224    /// regardless of whether a WFI or WFE instruction, or the sleep-on-exit functionality,
225    /// caused the entry to sleep mode.
226    /// However, all sleep features are implementation defined and therefore when
227    /// this counter counts is implementation defined.
228    #[cfg(not(armv6m))]
229    #[inline]
230    pub fn sleep_count() -> u8 {
231        // NOTE(unsafe) atomic read with no side effects
232        unsafe { (*Self::PTR).sleepcnt.read() as u8 }
233    }
234
235    /// Set the sleep count
236    #[cfg(not(armv6m))]
237    #[inline]
238    pub fn set_sleep_count(&mut self, count: u8) {
239        unsafe { self.sleepcnt.write(count as u32) }
240    }
241
242    /// Get the additional cycles required to execute all load or store instructions
243    #[cfg(not(armv6m))]
244    #[inline]
245    pub fn lsu_count() -> u8 {
246        // NOTE(unsafe) atomic read with no side effects
247        unsafe { (*Self::PTR).lsucnt.read() as u8 }
248    }
249
250    /// Set the lsu count
251    #[cfg(not(armv6m))]
252    #[inline]
253    pub fn set_lsu_count(&mut self, count: u8) {
254        unsafe { self.lsucnt.write(count as u32) }
255    }
256
257    /// Get the folded instruction count
258    ///
259    /// Increments on each instruction that takes 0 cycles.
260    #[cfg(not(armv6m))]
261    #[inline]
262    pub fn fold_count() -> u8 {
263        // NOTE(unsafe) atomic read with no side effects
264        unsafe { (*Self::PTR).foldcnt.read() as u8 }
265    }
266
267    /// Set the folded instruction count
268    #[cfg(not(armv6m))]
269    #[inline]
270    pub fn set_fold_count(&mut self, count: u8) {
271        unsafe { self.foldcnt.write(count as u32) }
272    }
273}
cortex_m/peripheral/dwt.rs

cortex_m/peripheral/
dwt.rs
