Struct cortex_m::peripheral::cpuid::Registers [−][src]
#[repr(C)]pub struct Registers { pub base: RO<u32>, pub pfr: [RO<u32>; 2], pub dfr: RO<u32>, pub afr: RO<u32>, pub mmfr: [RO<u32>; 4], pub isar: [RO<u32>; 5], pub clidr: RO<u32>, pub ctr: RO<u32>, pub ccsidr: RO<u32>, pub csselr: RO<u32>, // some fields omitted }
Registers
Fields
base: RO<u32>
CPUID base
pfr: [RO<u32>; 2]
Processor Feature
dfr: RO<u32>
Debug Feature
afr: RO<u32>
Auxiliary Feature
mmfr: [RO<u32>; 4]
Memory Model Feature
isar: [RO<u32>; 5]
Instruction Set Attribute
clidr: RO<u32>
Cache Level ID
ctr: RO<u32>
Cache Type
ccsidr: RO<u32>
Cache Size ID
csselr: RO<u32>
Cache Size Selection