cortex_m_interrupt/
nvic.rs

1use cortex_m::{interrupt::InterruptNumber, peripheral::NVIC};
2
3use crate::InterruptRegistration;
4
5/// An [`NVIC`] interrupt registration.
6///
7/// The proc-macro [`take_nvic_interrupt`] should be used to create
8/// an implementor of this trait.
9///
10/// [`take_nvic_interrupt`]: super::take_nvic_interrupt
11pub trait NvicInterruptRegistration<T: InterruptNumber>: InterruptRegistration {
12    /// The interrupt number that this [`NvicInterruptRegistration`] is associated with.
13    const INTERRUPT_NUMBER: T;
14
15    fn number(&self) -> T {
16        Self::INTERRUPT_NUMBER
17    }
18}
19
20/// Determine the amount of priority bits available on the current MCU.
21///
22/// This function determines the amount of priority bits available on a Cortex-M MCU by
23/// setting the priority of an interrupt to the maximum value `0xFF`, and reading the resulting
24/// priority.
25///
26/// The count of leading ones in the resulting value indicates the amount of
27/// priority-level bits available.
28///
29/// After performing this calculation, the priority of the placeholder interrupt is **not** restored.
30///
31/// It is guaranteed that all non-implemented priority bits will be read back as zero for any
32/// NVIC implementation that conforms to the [GIC] (see section 3.5.1), which includes at least all
33/// [armv7m] (see section B1.5.4) and [armv6m] (see section B3.4) cores.
34///
35/// # Safety
36/// This function should only be called from a critical section, as it alters the priority
37/// of an interrupt.
38///
39/// The caller must restore the priority of `placeholder_interrupt` to a known-and-valid priority after
40/// calling this function, as [`determine_prio_bits`] does not restore the overwritten priority.
41///
42/// [GIC]: https://documentation-service.arm.com/static/5f8ff196f86e16515cdbf969
43/// [armv7m]: https://documentation-service.arm.com/static/606dc36485368c4c2b1bf62f
44/// [armv6m]: https://documentation-service.arm.com/static/5f8ff05ef86e16515cdbf826
45pub unsafe fn determine_prio_bits<T: InterruptNumber>(
46    nvic: &mut NVIC,
47    placeholder_interrupt: T,
48) -> u8 {
49    nvic.set_priority(placeholder_interrupt, 0xFF);
50    let written_prio = NVIC::get_priority(placeholder_interrupt);
51
52    let prio_bits = written_prio.leading_ones();
53
54    prio_bits as u8
55}
56
57/// Convert a logical priority (where higher priority number = higher priority level) to
58/// a hardware priority level (where lower priority number = higher priority level).
59///
60/// `None` is returned if the priority `logical` is greater than the amount of priority
61/// levels supported by an NVIC with `nvic_prio_bits`, i.e. `logical > (1 << nvic_prio_bits)`.
62///
63/// Taken from [`cortex_m_rtic`]
64///
65/// See RTIC-LICENSE-MIT for the license.
66///
67/// [`cortex_m_rtic`]: https://crates.io/crates/cortex-m-rtic
68#[inline]
69#[must_use]
70pub fn logical2hw(logical: core::num::NonZeroU8, nvic_prio_bits: u8) -> Option<u8> {
71    if logical.get() <= 1 << nvic_prio_bits {
72        Some(((1u8 << nvic_prio_bits) - logical.get()) << (8 - nvic_prio_bits))
73    } else {
74        None
75    }
76}
77
78#[cfg(test)]
79#[test]
80fn test() {
81    for i in 1..=24 {
82        if i <= 16 {
83            // Verify that we compute the correct priority
84            // for all "valid" values.
85            assert_eq!(
86                logical2hw(core::num::NonZeroU8::new(i).unwrap(), 4),
87                Some(((1u8 << 4) - i) << (8 - 4))
88            );
89        } else {
90            // Verify that no priority is returned if it is outside of the
91            // priority range
92            assert_eq!(logical2hw(core::num::NonZeroU8::new(i).unwrap(), 4), None);
93        }
94    }
95}
cortex_m_interrupt/nvic.rs

cortex_m_interrupt/
nvic.rs
