Crate cortex_m_asm[][src]


Read the APSR register.

Write the BASEPRI_MAX register.

Write to BASEPRI_MAX on Cortex-M7 r0p1 CPUs. Accounts for erratum 837070.

Read the BASEPRI register.

Write the BASEPRI register.

Write to BASEPRI on Cortex-M7 r0p1 CPUs. Accounts for erratum 837070.

Puts the processor in Debug state. Debuggers can pick this up as a “breakpoint”.

Set CONTROL.SPSEL to 0, write msp to MSP, branch to rv.

Reads the CONTROL register.

Writes the CONTROL register.

Disables all interrupts.

Enables all interrupts.

Blocks the program for at least cycles CPU cycles.

Data Memory Barrier

Data Synchronization Barrier

Enable DCACHE.

Enable ICACHE.

Read the FAULTMASK register.

Reads the FPSCR register.

Writes to the FPSCR register.

Instruction Synchronization Barrier

Read the LR register.

Write to the LR register.

Read the MSP register.

Write the MSP register.

A no-operation. Useful to prevent delay loops from being optimized away.

Read the PC register.

Write to the PC register.

Read the PRIMASK register.

Read the PSP register.

Write the PSP register.

Send Event.

Semihosting syscall.

Generate an Undefined Instruction exception.

Wait For Event.

Wait For Interrupt.