cortex_ar/register/
dccmvau.rs

1//! DCCMVAU (*Clean Data Cache Or Unified Cache Line by MVA to Point of Unification.*)
2use crate::register::{SysReg, SysRegWrite};
3
4#[derive(Debug, Copy, Clone)]
5#[cfg_attr(feature = "defmt", derive(defmt::Format))]
6#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
7pub struct Dccmvau(pub u32);
8
9impl Dccmvau {
10    #[inline]
11    pub const fn new(addr: u32) -> Self {
12        Self(addr)
13    }
14}
15impl SysReg for Dccmvau {
16    const CP: u32 = 15;
17    const CRN: u32 = 7;
18    const OP1: u32 = 0;
19    const CRM: u32 = 11;
20    const OP2: u32 = 1;
21}
22
23impl crate::register::SysRegWrite for Dccmvau {}
24
25impl Dccmvau {
26    #[inline]
27    /// Writes DCCMVAU (*Clean Data Cache Or Unified Cache Line by MVA to Point of Unification.*)
28    ///
29    /// # Safety
30    ///
31    /// Ensure that this value is appropriate for this register. Generally, the address passed
32    /// to the write call should be aligned to the cache line size.
33    pub unsafe fn write(value: Self) {
34        unsafe {
35            <Self as SysRegWrite>::write_raw(value.0);
36        }
37    }
38}
cortex_ar/register/dccmvau.rs

cortex_ar/register/
dccmvau.rs
