cortex_ar/register/
csselr.rs

1//! Code for managing CSSELR (*Cache Size Selection Register*)
2use arbitrary_int::u3;
3
4use crate::register::{SysReg, SysRegRead, SysRegWrite};
5
6#[bitbybit::bitenum(u1, exhaustive = true)]
7#[derive(Debug, PartialEq, Eq)]
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10pub enum CacheType {
11    DataOrUnified = 0,
12    Instruction = 1,
13}
14
15/// CSSELR (*Cache Size Selection Register*)
16#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
17#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
18#[derive(PartialEq, Eq)]
19pub struct Csselr {
20    /// 0 for L1 cache, 1 for L2, etc.
21    #[bits(1..=3, rw)]
22    level: u3,
23    #[bit(0, rw)]
24    cache_type: CacheType,
25}
26
27impl SysReg for Csselr {
28    const CP: u32 = 15;
29    const CRN: u32 = 0;
30    const OP1: u32 = 2;
31    const CRM: u32 = 0;
32    const OP2: u32 = 0;
33}
34impl crate::register::SysRegRead for Csselr {}
35impl Csselr {
36    #[inline]
37    /// Reads CSSELR (*Cache Size Selection Register*)
38    pub fn read() -> Csselr {
39        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
40    }
41}
42impl crate::register::SysRegWrite for Csselr {}
43impl Csselr {
44    #[inline]
45    /// Writes CSSELR (*Cache Size Selection Register*)
46    ///
47    /// # Safety
48    ///
49    /// Ensure that this value is appropriate for this register
50    pub unsafe fn write(value: Self) {
51        unsafe {
52            <Self as SysRegWrite>::write_raw(value.raw_value());
53        }
54    }
55}
cortex_ar/register/csselr.rs

cortex_ar/register/
csselr.rs
