cortex_ar/register/armv8r/
vbar.rs

1//! Code for managing VBAR (*Vector Base Address Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// VBAR (*Vector Base Address Register*)
6///
7/// There is no `modify` method because this register holds a single 32-bit address.
8#[derive(Clone, Copy, PartialEq, Eq)]
9#[repr(transparent)]
10#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
11pub struct Vbar(pub *mut u32);
12
13impl SysReg for Vbar {
14    const CP: u32 = 15;
15    const CRN: u32 = 12;
16    const OP1: u32 = 0;
17    const CRM: u32 = 0;
18    const OP2: u32 = 0;
19}
20
21impl SysRegRead for Vbar {}
22
23impl SysRegWrite for Vbar {}
24
25impl Vbar {
26    /// Read VBAR (*Vector Base Address Register*)
27    #[inline]
28    pub fn read() -> Vbar {
29        // Safety: Reading this register has no side-effects and is atomic
30        unsafe { Self(<Self as SysRegRead>::read_raw() as *mut u32) }
31    }
32
33    /// Write VBAR (*Vector Base Address Register*)
34    ///
35    /// # Safety
36    ///
37    /// You must supply a correctly-aligned address of a valid Arm Cortex-R
38    /// Vector Table.
39    #[inline]
40    pub unsafe fn write(value: Self) {
41        // Safety: Writing this register is atomic
42        unsafe {
43            <Self as SysRegWrite>::write_raw(value.0 as u32);
44        }
45    }
46}
47
48impl core::fmt::Debug for Vbar {
49    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
50        write!(f, "VBAR {{ {:010p} }}", self.0)
51    }
52}
53
54#[cfg(feature = "defmt")]
55impl defmt::Format for Vbar {
56    fn format(&self, f: defmt::Formatter) {
57        defmt::write!(f, "VBAR {{ 0x{=usize:08x} }}", self.0 as usize)
58    }
59}
cortex_ar/register/armv8r/vbar.rs

cortex_ar/register/armv8r/
vbar.rs
