cortex_ar/register/armv8r/
prlar.rs

1//! Code for managing PRLAR (*Protection Region Limit Address Register*)
2
3use arbitrary_int::{u26, u3};
4
5use crate::register::{SysReg, SysRegRead, SysRegWrite};
6
7/// PRLAR (*Protection Region Limit Address Register*)
8#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
9pub struct Prlar {
10    /// Length of region
11    #[bits(6..=31, rw)]
12    limit: u26,
13    /// Which MAIR attribute to use
14    #[bits(1..=3, rw)]
15    mair: u3,
16    /// Is region enabled?
17    #[bits(0..=0, rw)]
18    enabled: bool,
19}
20
21impl SysReg for Prlar {
22    const CP: u32 = 15;
23    const CRN: u32 = 6;
24    const OP1: u32 = 0;
25    const CRM: u32 = 3;
26    const OP2: u32 = 1;
27}
28impl crate::register::SysRegRead for Prlar {}
29impl Prlar {
30    #[inline]
31    /// Reads PRLAR (*Protection Region Limit Address Register*)
32    pub fn read() -> Prlar {
33        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
34    }
35}
36impl crate::register::SysRegWrite for Prlar {}
37impl Prlar {
38    #[inline]
39    /// Writes PRLAR (*Protection Region Limit Address Register*)
40    pub fn write(value: Self) {
41        unsafe {
42            <Self as SysRegWrite>::write_raw(value.raw_value());
43        }
44    }
45}
cortex_ar/register/armv8r/prlar.rs

cortex_ar/register/armv8r/
prlar.rs
