cortex_ar/register/armv8r/
hvbar.rs

1//! Code for HVBAR (*Hyp Vector Base Address Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// HVBAR (*Hyp Vector Base Address Register*)
6///
7/// There is no `modify` method because this register holds a single 32-bit address.
8///
9/// This is only available in EL2.
10#[derive(Clone, Copy, PartialEq, Eq)]
11#[repr(transparent)]
12pub struct Hvbar(*mut u32);
13
14impl SysReg for Hvbar {
15    const CP: u32 = 15;
16    const CRN: u32 = 12;
17    const OP1: u32 = 4;
18    const CRM: u32 = 0;
19    const OP2: u32 = 0;
20}
21
22impl SysRegRead for Hvbar {}
23
24impl SysRegWrite for Hvbar {}
25
26impl Hvbar {
27    /// Read HVBAR (*Hyp Vector Base Address Register*)
28    #[inline]
29    pub fn read() -> Hvbar {
30        // Safety: Reading this register has no side-effects and is atomic
31        unsafe { Self(<Self as SysRegRead>::read_raw() as *mut u32) }
32    }
33
34    /// Write HVBAR (*Hyp Vector Base Address Register*)
35    ///
36    /// # Safety
37    ///
38    /// You must supply a correctly-aligned address of a valid Arm Cortex-R
39    /// Vector Table.
40    #[inline]
41    pub unsafe fn write(value: Self) {
42        // Safety: Writing this register is atomic
43        unsafe {
44            <Self as SysRegWrite>::write_raw(value.0 as u32);
45        }
46    }
47}
48
49impl core::fmt::Debug for Hvbar {
50    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
51        write!(f, "HVBAR {{ {:010p} }}", self.0)
52    }
53}
54
55#[cfg(feature = "defmt")]
56impl defmt::Format for Hvbar {
57    fn format(&self, f: defmt::Formatter) {
58        defmt::write!(f, "HVBAR {{ 0x{=usize:08x} }}", self.0 as usize)
59    }
60}
cortex_ar/register/armv8r/hvbar.rs

cortex_ar/register/armv8r/
hvbar.rs
