cortex_ar/register/armv8r/
hprlar0.rs

1//! Code for managing HPRLAR0 (*Hyp Protection Region Limit Address Register 0*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// HPRLAR0 (*Hyp Protection Region Limit Address Register 0*)
6#[derive(Debug, Copy, Clone)]
7#[cfg_attr(feature = "defmt", derive(defmt::Format))]
8#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
9pub struct Hprlar0(pub u32);
10impl SysReg for Hprlar0 {
11    const CP: u32 = 15;
12    const CRN: u32 = 6;
13    const OP1: u32 = 4;
14    const CRM: u32 = 8;
15    const OP2: u32 = 1;
16}
17impl crate::register::SysRegRead for Hprlar0 {}
18impl Hprlar0 {
19    #[inline]
20    /// Reads HPRLAR0 (*Hyp Protection Region Limit Address Register 0*)
21    pub fn read() -> Hprlar0 {
22        unsafe { Self(<Self as SysRegRead>::read_raw()) }
23    }
24}
25impl crate::register::SysRegWrite for Hprlar0 {}
26impl Hprlar0 {
27    #[inline]
28    /// Writes HPRLAR0 (*Hyp Protection Region Limit Address Register 0*)
29    ///
30    /// # Safety
31    ///
32    /// Ensure that this value is appropriate for this register
33    pub unsafe fn write(value: Self) {
34        unsafe {
35            <Self as SysRegWrite>::write_raw(value.0);
36        }
37    }
38}
cortex_ar/register/armv8r/hprlar0.rs

cortex_ar/register/armv8r/
hprlar0.rs
