cortex_ar/register/armv8r/
hactlr2.rs

1//! Code for managing HACTLR2 (*Hyp Auxiliary Control Register 2*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// HACTLR2 (*Hyp Auxiliary Control Register 2*)
6#[derive(Debug, Copy, Clone)]
7#[cfg_attr(feature = "defmt", derive(defmt::Format))]
8#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
9pub struct Hactlr2(pub u32);
10impl SysReg for Hactlr2 {
11    const CP: u32 = 15;
12    const CRN: u32 = 1;
13    const OP1: u32 = 4;
14    const CRM: u32 = 0;
15    const OP2: u32 = 3;
16}
17impl crate::register::SysRegRead for Hactlr2 {}
18impl Hactlr2 {
19    #[inline]
20    /// Reads HACTLR2 (*Hyp Auxiliary Control Register 2*)
21    pub fn read() -> Hactlr2 {
22        unsafe { Self(<Self as SysRegRead>::read_raw()) }
23    }
24}
25impl crate::register::SysRegWrite for Hactlr2 {}
26impl Hactlr2 {
27    #[inline]
28    /// Writes HACTLR2 (*Hyp Auxiliary Control Register 2*)
29    ///
30    /// # Safety
31    ///
32    /// Ensure that this value is appropriate for this register
33    pub unsafe fn write(value: Self) {
34        unsafe {
35            <Self as SysRegWrite>::write_raw(value.0);
36        }
37    }
38}
cortex_ar/register/armv8r/hactlr2.rs

cortex_ar/register/armv8r/
hactlr2.rs
