cortex_ar/register/armv8r/
cntp_tval.rs

1//! Code for managing CNTP_TVAL (*Physical Counter-timer TimerValue Register*)
2
3use crate::register::{SysReg, SysRegRead, SysRegWrite};
4
5/// CNTP_TVAL (*Physical Counter-timer TimerValue Register*)
6#[derive(Debug, Copy, Clone)]
7#[cfg_attr(feature = "defmt", derive(defmt::Format))]
8#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
9pub struct CntpTval(pub u32);
10impl SysReg for CntpTval {
11    const CP: u32 = 15;
12    const CRN: u32 = 14;
13    const OP1: u32 = 0;
14    const CRM: u32 = 2;
15    const OP2: u32 = 0;
16}
17
18impl SysRegRead for CntpTval {}
19
20impl CntpTval {
21    #[inline]
22    /// Reads CNTP_TVAL (*Physical Counter-timer TimerValue Register*)
23    pub fn read() -> CntpTval {
24        unsafe { Self(<Self as SysRegRead>::read_raw()) }
25    }
26}
27
28impl SysRegWrite for CntpTval {}
29
30impl CntpTval {
31    #[inline]
32    /// Writes CNTP_TVAL (*Physical Counter-timer TimerValue Register*)
33    pub fn write(value: Self) {
34        unsafe {
35            <Self as SysRegWrite>::write_raw(value.0);
36        }
37    }
38}
cortex_ar/register/armv8r/cntp_tval.rs

cortex_ar/register/armv8r/
cntp_tval.rs
