cortex_ar/register/
mod.rs

1//! Access registers in Armv7-R and Armv8-R
2
3pub mod actlr;
4pub mod actlr2;
5pub mod adfsr;
6pub mod aidr;
7pub mod aifsr;
8pub mod amair0;
9pub mod amair1;
10pub mod bpiall;
11pub mod ccsidr;
12pub mod clidr;
13pub mod contextidr;
14pub mod cpacr;
15pub mod cpsr;
16pub mod csselr;
17pub mod ctr;
18pub mod dc_sw_ops;
19pub mod dccimvac;
20pub mod dccisw;
21pub mod dccmvac;
22pub mod dccmvau;
23pub mod dccsw;
24pub mod dcimvac;
25pub mod dcisw;
26pub mod dfar;
27pub mod dfsr;
28pub mod dlr;
29pub mod dracr;
30pub mod drbar;
31pub mod drsr;
32pub mod dspsr;
33pub mod fcseidr;
34pub mod icc_pmr;
35pub mod id_afr0;
36pub mod id_dfr0;
37pub mod id_isar0;
38pub mod id_isar1;
39pub mod id_isar2;
40pub mod id_isar3;
41pub mod id_isar4;
42pub mod id_isar5;
43pub mod id_mmfr0;
44pub mod id_mmfr1;
45pub mod id_mmfr2;
46pub mod id_mmfr3;
47pub mod id_mmfr4;
48pub mod id_pfr0;
49pub mod id_pfr1;
50pub mod ifar;
51pub mod ifsr;
52pub mod imp;
53pub mod iracr;
54pub mod irbar;
55pub mod irsr;
56pub mod mair0;
57pub mod mair1;
58pub mod midr;
59pub mod mpidr;
60pub mod mpuir;
61pub mod nsacr;
62pub mod par;
63pub mod pmccfiltr;
64pub mod pmccntr;
65pub mod pmceid0;
66pub mod pmceid1;
67pub mod pmcntenclr;
68pub mod pmcntenset;
69pub mod pmcr;
70pub mod pmevcntr0;
71pub mod pmevcntr1;
72pub mod pmevcntr2;
73pub mod pmevcntr3;
74pub mod pmevtyper0;
75pub mod pmevtyper1;
76pub mod pmevtyper2;
77pub mod pmevtyper3;
78pub mod pmintenclr;
79pub mod pmintenset;
80pub mod pmovsr;
81pub mod pmovsset;
82pub mod pmselr;
83pub mod pmswinc;
84pub mod pmuserenr;
85pub mod pmxevcntr;
86pub mod pmxevtyper;
87pub mod revidr;
88pub mod rgnr;
89pub mod rvbar;
90pub mod sctlr;
91pub mod tcmtr;
92pub mod tlbiall;
93pub mod tlbtr;
94pub mod tpidrprw;
95pub mod tpidruro;
96pub mod tpidrurw;
97pub mod vmpidr;
98pub mod vpidr;
99pub mod vsctlr;
100
101pub use actlr::Actlr;
102pub use actlr2::Actlr2;
103pub use adfsr::Adfsr;
104pub use aidr::Aidr;
105pub use aifsr::Aifsr;
106pub use amair0::Amair0;
107pub use amair1::Amair1;
108pub use bpiall::BpIAll;
109pub use ccsidr::Ccsidr;
110pub use clidr::Clidr;
111pub use contextidr::Contextidr;
112pub use cpacr::Cpacr;
113pub use cpsr::Cpsr;
114pub use csselr::Csselr;
115pub use ctr::Ctr;
116pub use dccimvac::Dccimvac;
117pub use dccisw::Dccisw;
118pub use dccmvac::Dccmvac;
119pub use dccmvau::Dccmvau;
120pub use dccsw::Dccsw;
121pub use dcimvac::Dcimvac;
122pub use dcisw::Dcisw;
123pub use dfar::Dfar;
124pub use dfsr::Dfsr;
125pub use dlr::Dlr;
126pub use dracr::Dracr;
127pub use drbar::Drbar;
128pub use drsr::Drsr;
129pub use dspsr::Dspsr;
130pub use fcseidr::Fcseidr;
131pub use icc_pmr::IccPmr;
132pub use id_afr0::IdAfr0;
133pub use id_dfr0::IdDfr0;
134pub use id_isar0::IdIsar0;
135pub use id_isar1::IdIsar1;
136pub use id_isar2::IdIsar2;
137pub use id_isar3::IdIsar3;
138pub use id_isar4::IdIsar4;
139pub use id_isar5::IdIsar5;
140pub use id_mmfr0::IdMmfr0;
141pub use id_mmfr1::IdMmfr1;
142pub use id_mmfr2::IdMmfr2;
143pub use id_mmfr3::IdMmfr3;
144pub use id_mmfr4::IdMmfr4;
145pub use id_pfr0::IdPfr0;
146pub use id_pfr1::IdPfr1;
147pub use ifar::Ifar;
148pub use ifsr::Ifsr;
149pub use iracr::Iracr;
150pub use irbar::Irbar;
151pub use irsr::Irsr;
152pub use mair0::Mair0;
153pub use mair1::Mair1;
154pub use midr::Midr;
155pub use mpidr::Mpidr;
156pub use mpuir::Mpuir;
157pub use nsacr::Nsacr;
158pub use par::Par;
159pub use pmccfiltr::Pmccfiltr;
160pub use pmccntr::Pmccntr;
161pub use pmceid0::Pmceid0;
162pub use pmceid1::Pmceid1;
163pub use pmcntenclr::Pmcntenclr;
164pub use pmcntenset::Pmcntenset;
165pub use pmcr::Pmcr;
166pub use pmevcntr0::Pmevcntr0;
167pub use pmevcntr1::Pmevcntr1;
168pub use pmevcntr2::Pmevcntr2;
169pub use pmevcntr3::Pmevcntr3;
170pub use pmevtyper0::Pmevtyper0;
171pub use pmevtyper1::Pmevtyper1;
172pub use pmevtyper2::Pmevtyper2;
173pub use pmevtyper3::Pmevtyper3;
174pub use pmintenclr::Pmintenclr;
175pub use pmintenset::Pmintenset;
176pub use pmovsr::Pmovsr;
177pub use pmovsset::Pmovsset;
178pub use pmselr::Pmselr;
179pub use pmswinc::Pmswinc;
180pub use pmuserenr::Pmuserenr;
181pub use pmxevcntr::Pmxevcntr;
182pub use pmxevtyper::Pmxevtyper;
183pub use revidr::Revidr;
184pub use rgnr::Rgnr;
185pub use rvbar::Rvbar;
186pub use sctlr::Sctlr;
187pub use tcmtr::Tcmtr;
188pub use tlbiall::TlbIAll;
189pub use tlbtr::Tlbtr;
190pub use tpidrprw::Tpidrprw;
191pub use tpidruro::Tpidruro;
192pub use tpidrurw::Tpidrurw;
193pub use vmpidr::Vmpidr;
194pub use vpidr::Vpidr;
195pub use vsctlr::Vsctlr;
196
197#[cfg(any(test, doc, arm_architecture = "v8-r"))]
198pub mod armv8r;
199#[cfg(any(test, doc, arm_architecture = "v8-r"))]
200pub use armv8r::*;
201
202pub use imp::*;
203
204/// Describes a 32-bit System Register
205pub trait SysReg {
206    /// Which Co-Processor (e.g. 15 for CP15) is this register in?
207    const CP: u32;
208    /// Which CRn argument (e.g. 0 for c0) accesses this register
209    const CRN: u32;
210    /// Which OP1 argument accesses this register
211    const OP1: u32;
212    /// Which CRm argument (e.g. 1 for c1) accesses this register
213    const CRM: u32;
214    /// Which OP2 argument accesses this register
215    const OP2: u32;
216}
217
218/// 32-bit Readable System Registers
219pub trait SysRegRead: SysReg {
220    /// Read a value from this 32-bit register
221    ///
222    /// # Safety
223    ///
224    /// You need to read the Architecture Reference Manual because this read
225    /// may have side-effects.
226    #[inline]
227    unsafe fn read_raw() -> u32 {
228        let r: u32;
229        #[cfg(target_arch = "arm")]
230        unsafe {
231            core::arch::asm!(
232                "mrc p{cp}, {op1}, {reg}, c{crn}, c{crm}, {op2}",
233                cp = const Self::CP,
234                op1 = const Self::OP1,
235                reg = out(reg) r,
236                crn = const Self::CRN,
237                crm = const Self::CRM,
238                op2 = const Self::OP2,
239                options(nomem, nostack, preserves_flags)
240            );
241        }
242        #[cfg(not(target_arch = "arm"))]
243        {
244            r = 0;
245        }
246        r
247    }
248}
249
250/// Writable 32-bit System Registers
251pub trait SysRegWrite: SysReg {
252    /// Write a value to this 32-bit register
253    ///
254    /// # Safety
255    ///
256    /// You need to read the Architecture Reference Manual to verify that you are
257    /// writing valid data here.
258    #[inline]
259    unsafe fn write_raw(_value: u32) {
260        #[cfg(target_arch = "arm")]
261        unsafe {
262            core::arch::asm!(
263                "mcr p{cp}, {op1}, {reg}, c{crn}, c{crm}, {op2}",
264                cp = const Self::CP,
265                op1 = const Self::OP1,
266                reg = in(reg) _value,
267                crn = const Self::CRN,
268                crm = const Self::CRM,
269                op2 = const Self::OP2,
270                options(nomem, nostack, preserves_flags)
271            );
272        }
273    }
274}
275
276/// Describes a 64-bit System Register
277pub trait SysReg64 {
278    /// Which Co-Processor (e.g. 15 for CP15) is this register in?
279    const CP: u32;
280    /// Which OP1 argument accesses this register
281    const OP1: u32;
282    /// Which CRm argument (e.g. 1 for c1) accesses this register
283    const CRM: u32;
284}
285
286/// 64-bit Readable System Registers
287pub trait SysRegRead64: SysReg64 {
288    /// Read a value from this 64-bit register
289    ///
290    /// # Safety
291    ///
292    /// You need to read the Architecture Reference Manual because this read
293    /// may have side-effects.
294    #[inline]
295    unsafe fn read_raw() -> u64 {
296        let r_lo: u32;
297        let r_hi: u32;
298        #[cfg(target_arch = "arm")]
299        unsafe {
300            core::arch::asm!(
301                "mrrc p{cp}, {op1}, {rt}, {rt2}, c{crm}",
302                cp = const Self::CP,
303                op1 = const Self::OP1,
304                rt = out(reg) r_lo,
305                rt2 = out(reg) r_hi,
306                crm = const Self::CRM,
307                options(nomem, nostack, preserves_flags)
308            );
309        }
310        #[cfg(not(target_arch = "arm"))]
311        {
312            r_lo = 0;
313            r_hi = 0;
314        }
315        ((r_hi as u64) << 32) | (r_lo as u64)
316    }
317}
318
319/// Writable 64-bit System Registers
320pub trait SysRegWrite64: SysReg64 {
321    /// Write a value to this 64-bit register
322    ///
323    /// # Safety
324    ///
325    /// You need to read the Architecture Reference Manual to verify that you are
326    /// writing valid data here.
327    #[inline]
328    unsafe fn write_raw(_value: u64) {
329        #[cfg(target_arch = "arm")]
330        unsafe {
331            let r_lo = _value as u32;
332            let r_hi = (_value >> 32) as u32;
333            core::arch::asm!(
334                "mcrr p{cp}, {op1}, {rt}, {rt2}, c{crm}",
335                cp = const Self::CP,
336                op1 = const Self::OP1,
337                rt = in(reg) r_lo,
338                rt2 = in(reg) r_hi,
339                crm = const Self::CRM,
340                options(nomem, nostack, preserves_flags)
341            );
342        }
343    }
344}
cortex_ar/register/mod.rs

cortex_ar/register/
mod.rs
