cortex_ar/register/
dcisw.rs

1//! DCISW (*Invalidate Data or Unified Cache line by Set/Way.*)
2
3use arbitrary_int::u3;
4
5use crate::register::{SysReg, SysRegWrite};
6
7#[derive(Debug, Copy, Clone)]
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10pub struct Dcisw(pub u32);
11
12impl Dcisw {
13    /// Create DCISW value for cache invalidation by set and way.
14    ///
15    /// ## Generics
16    ///
17    /// - A: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
18    ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
19    ///   3.
20    /// - N: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
21    ///   5.
22    #[inline]
23    pub const fn new<const A: usize, const N: usize>(way: u8, set: u16, level: u3) -> Self {
24        Self(super::dc_sw_ops::new::<A, N>(way, set, level))
25    }
26
27    /// Create DCISW value for cache invalidation by set and way.
28    /// Returns [None] on invalid input.
29    ///
30    /// # Arguments
31    ///
32    /// - a: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
33    ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
34    ///   3.
35    /// - n: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
36    ///   5.
37    #[inline]
38    pub const fn new_with_offsets(a: usize, way: u8, n: usize, set: u16, level: u3) -> Self {
39        Self(super::dc_sw_ops::new_with_offsets(a, way, n, set, level))
40    }
41}
42impl SysReg for Dcisw {
43    const CP: u32 = 15;
44    const CRN: u32 = 7;
45    const OP1: u32 = 0;
46    const CRM: u32 = 6;
47    const OP2: u32 = 2;
48}
49
50impl crate::register::SysRegWrite for Dcisw {}
51
52impl Dcisw {
53    #[inline]
54    /// Writes DCSW (*Invalidate Data or Unified Cache line by Set/Way.*)
55    ///
56    /// # Safety
57    ///
58    /// Ensure that this value is appropriate for this register
59    pub unsafe fn write(value: Self) {
60        unsafe {
61            <Self as SysRegWrite>::write_raw(value.0);
62        }
63    }
64}
cortex_ar/register/dcisw.rs

cortex_ar/register/
dcisw.rs
