cortex_a/registers/
esr_el2.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7//   - Berkus Decker <berkus+github@metta.systems>
8//   - Bradley Landherr <landhb@users.noreply.github.com>
9
10//! Exception Syndrome Register - EL2
11//!
12//! Holds syndrome information for an exception taken to EL2.
13
14use tock_registers::{interfaces::Readable, register_bitfields};
15
16register_bitfields! {u64,
17    pub ESR_EL2 [
18
19        /// Reserved
20        RES0 OFFSET(37) NUMBITS(27) [],
21
22        /// Instruction Specific Syndrome 2. If a memory access generated by an ST64BV or ST64BV0
23        /// instruction generates a Data Abort for a Translation fault, Access flag fault, or
24        /// Permission fault, then this field holds register specifier, Xs.
25        ///
26        /// For any other Data Abort, this field is RES0.
27        ISS2 OFFSET(32) NUMBITS(5) [],
28
29        /// Exception Class. Indicates the reason for the exception that this register holds
30        /// information about.
31        ///
32        /// For each EC value, the table references a subsection that gives information about:
33        ///   - The cause of the exception, for example the configuration required to enable the
34        ///     trap.
35        ///   - The encoding of the associated ISS.
36        ///
37        /// Incomplete listing - to be done.
38        EC  OFFSET(26) NUMBITS(6) [
39            Unknown               = 0b00_0000,
40            TrappedWFIorWFE       = 0b00_0001,
41            TrappedMCRorMRC       = 0b00_0011, // A32
42            TrappedMCRRorMRRC     = 0b00_0100, // A32
43            TrappedMCRorMRC2      = 0b00_0101, // A32
44            TrappedLDCorSTC       = 0b00_0110, // A32
45            TrappedFP             = 0b00_0111,
46            TrappedMRRC           = 0b00_1100, // A32
47            BranchTarget          = 0b00_1101,
48            IllegalExecutionState = 0b00_1110,
49            SVC32                 = 0b01_0001, // A32
50            SVC64                 = 0b01_0101,
51            HVC64                 = 0b01_0110,
52            SMC64                 = 0b01_0111,
53            TrappedMsrMrs         = 0b01_1000,
54            TrappedSve            = 0b01_1001,
55            PointerAuth           = 0b01_1100,
56            InstrAbortLowerEL     = 0b10_0000,
57            InstrAbortCurrentEL   = 0b10_0001,
58            PCAlignmentFault      = 0b10_0010,
59            DataAbortLowerEL      = 0b10_0100,
60            DataAbortCurrentEL    = 0b10_0101,
61            SPAlignmentFault      = 0b10_0110,
62            TrappedFP32           = 0b10_1000, // A32
63            TrappedFP64           = 0b10_1100,
64            SError                = 0b10_1111,
65            BreakpointLowerEL     = 0b11_0000,
66            BreakpointCurrentEL   = 0b11_0001,
67            SoftwareStepLowerEL   = 0b11_0010,
68            SoftwareStepCurrentEL = 0b11_0011,
69            WatchpointLowerEL     = 0b11_0100,
70            WatchpointCurrentEL   = 0b11_0101,
71            Bkpt32                = 0b11_1000, // A32 BKTP instruction
72            Brk64                 = 0b11_1100  // A64 BRK instruction
73        ],
74
75        /// Instruction Length for synchronous exceptions.
76        IL  OFFSET(25) NUMBITS(1) [],
77
78        /// Instruction Specific Syndrome. Architecturally, this field can be defined independently
79        /// for each defined Exception class. However, in practice, some ISS encodings are used for
80        /// more than one Exception class.
81        ISS OFFSET(0)  NUMBITS(25) []
82    ]
83}
84
85pub struct Reg;
86
87impl Readable for Reg {
88    type T = u64;
89    type R = ESR_EL2::Register;
90
91    sys_coproc_read_raw!(u64, "ESR_EL2", "x");
92}
93
94pub const ESR_EL2: Reg = Reg {};
cortex_a/registers/esr_el2.rs

cortex_a/registers/
esr_el2.rs
