cortex_a/registers/
vtcr_el2.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6//   - Ali Saidi <alisaidi@amazon.com>
7
8//! Virtualization Translation Control Register - EL2
9//!
10//! Provides control of stage2 translation of EL0/1
11
12use tock_registers::{
13    interfaces::{Readable, Writeable},
14    register_bitfields,
15};
16
17register_bitfields! {u64,
18    pub VTCR_EL2 [
19        /// Hardware dirty flag update in stage2 translations when EL2 is enabled
20        HD OFFSET(22) NUMBITS(1) [
21            /// Stage2 hardware management of dirty state disabled
22            Disabled = 0,
23            /// Stage2 hardware management of dirty state enabled
24            Enabled = 1,
25        ],
26        /// Hardware access flag update in stage2 translations when EL2 is enabled
27        HA OFFSET(21) NUMBITS(1) [
28            /// Stage2 hardware management of access state disabled
29            Disabled = 0,
30            /// Stage2 hardware management of access state enabled
31            Enabled = 1,
32        ],
33        /// VMID Size
34        VS OFFSET(19) NUMBITS(1) [
35            /// 8-bit VMID
36            Bits8 = 0,
37            /// 16-bit VMID
38            Bits16 = 1,
39        ],
40        /// Physical Address size of the second stage of translation
41        PS OFFSET(16) NUMBITS(3) [
42            /// 32 bits, 4GB
43            PA_32B_4GB = 0b000,
44            /// 36 bits, 64GB
45            PA_36B_64GB = 0b001,
46            /// 40 bits, 1TB
47            PA_40B_1TB = 0b010,
48            /// 42 bits, 4TB
49            PA_42B_4TB = 0b011,
50            /// 44 bits, 16TB
51            PA_44B_16TB = 0b100,
52            /// 48 bits, 256TB
53            PA_48B_256TB = 0b101,
54            /// 52 bits, 4PB
55            PA_52B_4PB = 0b110,
56        ],
57        /// Granule size used for `VTTBR_EL2`
58        TG0 OFFSET(14) NUMBITS(2) [
59            /// Granule size of 4KB
60            Granule4KB = 0b00,
61            /// Granule size of 16KB
62            Granule16KB = 0b10,
63            /// Granule size of 64KB
64            Granule64KB = 0b01,
65        ],
66        /// Shareability attribute for memory associated with translation table
67        /// walks using `VTTBR_EL2` and `VSTTBR_EL2`
68        SH0 OFFSET(12) NUMBITS(2) [
69            /// Non-shareable
70            Non = 0b00,
71            /// Outer sharable
72            Outer = 0b10,
73            /// Inner sharable
74            Inner = 0b11,
75        ],
76        /// Outer cacheability attribute for memory associated with translation table
77        /// walks using `VTTBR_EL2` and `VSTTBR_EL2`
78        ORGN0 OFFSET(10) NUMBITS(2) [
79            /// Normal non-cacheable memory
80            NormalNC = 0b00,
81            /// Normal Write-back, Read-allocate, Write-allocate
82            NormalWBRAWA = 0b01,
83            /// Normal Write-through, Read-allocate, no Write-allocate
84            NormalWTRAnWA = 0b10,
85            /// Normal Write-back, Read-allocate, no Write-allocate
86            NormalWBRAnWA = 0b11,
87        ],
88        /// Inner cacheability attribute for memory associated with translation table
89        /// walks using `VTTBR_EL2` and `VSTTBR_EL2`
90        IRGN0 OFFSET(8) NUMBITS(2) [
91            /// Normal non-cacheable memory
92            NormalNC = 0b00,
93            /// Normal Write-back, Read-allocate, Write-allocate
94            NormalWBRAWA = 0b01,
95            /// Normal Write-through, Read-allocate, no Write-allocate
96            NormalWTRAnWA = 0b10,
97            /// Normal Write-back, Read-allocate, no Write-allocate
98            NormalWBRAnWA = 0b11,
99        ],
100        /// Starting level of the stage2 translation lookup
101        SL0 OFFSET(6) NUMBITS(2) [],
102        /// The size of the offest of the memory region addressed by the `VTTBR_EL2`
103        T0SZ OFFSET(0) NUMBITS(6) [],
104
105    ]
106}
107pub struct Reg;
108
109impl Readable for Reg {
110    type T = u64;
111    type R = VTCR_EL2::Register;
112
113    sys_coproc_read_raw!(u64, "VTCR_EL2", "x");
114}
115
116impl Writeable for Reg {
117    type T = u64;
118    type R = VTCR_EL2::Register;
119
120    sys_coproc_write_raw!(u64, "VTCR_EL2", "x");
121}
122
123pub const VTCR_EL2: Reg = Reg {};
124
cortex_a/registers/vtcr_el2.rs

cortex_a/registers/
vtcr_el2.rs
