cortex_a/registers/tcr_el2.rs
1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6// - Andre Richter <andre.o.richter@gmail.com>
7// - Bradley Landherr <landhb@users.noreply.github.com>
8
9//! Translation Control Register - EL2
10//!
11//! The control register for stage 1 of the EL2, or EL2&0 translation regime.
12
13use tock_registers::{
14 interfaces::{Readable, Writeable},
15 register_bitfields,
16};
17
18register_bitfields! {u64,
19 pub TCR_EL2 [
20
21 /// When FEAT_HAFDBS is implemented hardware can update the dirty flags in the stage1
22 /// descriptors
23 HD OFFSET(22) NUMBITS(1) [
24 Disable = 0,
25 Enable = 1,
26 ],
27
28 /// When FEAT_HAFDBS is implemented hardware can update the access flags in the stage1
29 /// descriptors
30 HA OFFSET(21) NUMBITS(1) [
31 Disable = 0,
32 Enable = 1,
33 ],
34
35 /// Top Byte ignored - indicates whether the top byte of an address is used for address
36 /// match for the TTBR0_EL2 region, or ignored and used for tagged addresses. Defined values
37 /// are:
38 ///
39 /// 0 Top Byte used in the address calculation.
40 ///
41 /// 1 Top Byte ignored in the address calculation.
42 ///
43 /// This affects addresses generated in EL2 using AArch64 where the address would be
44 /// translated by tables pointed to by TTBR0_EL2. It has an effect whether the EL2,
45 /// or EL2&0, translation regime is enabled or not.
46 ///
47 /// If ARMv8.3-PAuth is implemented and TCR_EL2.TBID1 is 1, then this field only applies to
48 /// Data accesses.
49 ///
50 /// If the value of TBI is 1, then bits[63:56] of that target address are also set to 0
51 /// before the address is stored in the PC, in the following cases:
52 ///
53 /// • A branch or procedure return within EL2.
54 /// • An exception taken to EL2.
55 /// • An exception return to EL2.
56 TBI OFFSET(20) NUMBITS(1) [
57 Used = 0,
58 Ignored = 1
59 ],
60
61 /// Physical Address Size.
62 ///
63 /// 000 32 bits, 4GiB.
64 /// 001 36 bits, 64GiB.
65 /// 010 40 bits, 1TiB.
66 /// 011 42 bits, 4TiB.
67 /// 100 44 bits, 16TiB.
68 /// 101 48 bits, 256TiB.
69 /// 110 52 bits, 4PB
70 ///
71 /// Other values are reserved.
72 ///
73 /// The reserved values behave in the same way as the 101 or 110 encoding, but software must
74 /// not rely on this property as the behavior of the reserved values might change in a
75 /// future revision of the architecture.
76 ///
77 /// The value 110 is permitted only if ARMv8.2-LPA is implemented and the translation
78 /// granule size is 64KiB.
79 ///
80 /// In an implementation that supports 52-bit PAs, if the value of this field is not 110 ,
81 /// then bits[51:48] of every translation table base address for the stage of translation
82 /// controlled by TCR_EL2 are 0000.
83 PS OFFSET(16) NUMBITS(3) [
84 Bits_32 = 0b000,
85 Bits_36 = 0b001,
86 Bits_40 = 0b010,
87 Bits_42 = 0b011,
88 Bits_44 = 0b100,
89 Bits_48 = 0b101,
90 Bits_52 = 0b110
91 ],
92
93 /// Granule size for the TTBR0_EL2.
94 ///
95 /// 0b00 4KiB
96 /// 0b01 64KiB
97 /// 0b10 16KiB
98 ///
99 /// Other values are reserved.
100 ///
101 /// If the value is programmed to either a reserved value, or a size that has not been
102 /// implemented, then the hardware will treat the field as if it has been programmed to an
103 /// IMPLEMENTATION DEFINED choice of the sizes that has been implemented for all purposes
104 /// other than the value read back from this register.
105 ///
106 /// It is IMPLEMENTATION DEFINED whether the value read back is the value programmed or the
107 /// value that corresponds to the size chosen.
108 TG0 OFFSET(14) NUMBITS(2) [
109 KiB_4 = 0b00,
110 KiB_64 = 0b01,
111 KiB_16 = 0b10
112 ],
113
114 /// Shareability attribute for memory associated with translation table walks using
115 /// TTBR0_EL2.
116 ///
117 /// 00 Non-shareable
118 /// 01 Reserved
119 /// 10 Outer Shareable
120 /// 11 Inner Shareable
121 ///
122 /// Other values are reserved.
123 SH0 OFFSET(12) NUMBITS(2) [
124 None = 0b00,
125 Outer = 0b10,
126 Inner = 0b11
127 ],
128
129 /// Outer cacheability attribute for memory associated with translation table walks using
130 /// TTBR0_EL2.
131 ///
132 /// 00 Normal memory, Outer Non-cacheable
133 ///
134 /// 01 Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable
135 ///
136 /// 10 Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable
137 ///
138 /// 11 Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable
139 ORGN0 OFFSET(10) NUMBITS(2) [
140 NonCacheable = 0b00,
141 WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01,
142 WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10,
143 WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11
144 ],
145
146 /// Inner cacheability attribute for memory associated with translation table walks using
147 /// TTBR0_EL2.
148 ///
149 /// 00 Normal memory, Inner Non-cacheable
150 ///
151 /// 01 Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable
152 ///
153 /// 10 Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable
154 ///
155 /// 11 Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable
156 IRGN0 OFFSET(8) NUMBITS(2) [
157 NonCacheable = 0b00,
158 WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01,
159 WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10,
160 WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11
161 ],
162
163
164 /// The size offset of the memory region addressed by TTBR0_EL2. The region size is
165 /// 2^(64-T0SZ) bytes.
166 ///
167 /// The maximum and minimum possible values for T0SZ depend on the level of translation
168 /// table and the memory translation granule size, as described in the AArch64 Virtual
169 /// Memory System Architecture chapter.
170 T0SZ OFFSET(0) NUMBITS(6) []
171 ]
172}
173
174pub struct Reg;
175
176impl Readable for Reg {
177 type T = u64;
178 type R = TCR_EL2::Register;
179
180 sys_coproc_read_raw!(u64, "TCR_EL2", "x");
181}
182
183impl Writeable for Reg {
184 type T = u64;
185 type R = TCR_EL2::Register;
186
187 sys_coproc_write_raw!(u64, "TCR_EL2", "x");
188}
189
190pub const TCR_EL2: Reg = Reg {};