cortex_a/registers/hcr_el2.rs
1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6// - Andre Richter <andre.o.richter@gmail.com>
7// - Bradley Landherr <landhb@users.noreply.github.com>
8// - Javier Alvarez <javier.alvarez@allthingsembedded.com>
9
10//! Hypervisor Configuration Register - EL2
11//!
12//! Provides configuration controls for virtualization, including defining
13//! whether various Non-secure operations are trapped to EL2.
14
15use tock_registers::{
16 interfaces::{Readable, Writeable},
17 register_bitfields,
18};
19
20register_bitfields! {u64,
21 pub HCR_EL2 [
22 /// When FEAT_S2FWB is implemented Forced Write-back changes the combined cachability of stage1
23 /// and stage2 attributes
24 FWB OFFSET(46) NUMBITS(1) [
25 /// Stage2 memory type and cacheability attributes are in bits[5:2] of the stage2 PTE
26 Disabled = 0,
27 /// Stage1 memory type can be overridden by Stage2 descriptor
28 Enabled = 1,
29 ],
30
31 /// Controls the use of instructions related to Pointer Authentication:
32 ///
33 /// - In EL0, when HCR_EL2.TGE==0 or HCR_EL2.E2H==0, and the associated SCTLR_EL1.En<N><M>==1.
34 /// - In EL1, the associated SCTLR_EL1.En<N><M>==1.
35 ///
36 /// Traps are reported using EC syndrome value 0x09. The Pointer Authentication instructions
37 /// trapped are:
38 ///
39 /// `AUTDA`, `AUTDB`, `AUTDZA`, `AUTDZB`, `AUTIA`, `AUTIA1716`, `AUTIASP`, `AUTIAZ`, `AUTIB`, `AUTIB1716`,
40 /// `AUTIBSP`, `AUTIBZ`, `AUTIZA`, `AUTIZB`, `PACGA`, `PACDA`, `PACDB`, `PACDZA`, `PACDZB`, `PACIA`,
41 /// `PACIA1716`, `PACIASP`, `PACIAZ`, `PACIB`, `PACIB1716`, `PACIBSP`, `PACIBZ`, `PACIZA`, `PACIZB`,
42 /// `RETAA`, `RETAB`, `BRAA`, `BRAB`, `BLRAA`, `BLRAB`, `BRAAZ`, `BRABZ`, `BLRAAZ`, `BLRABZ`,
43 /// `ERETAA`, `ERETAB`, `LDRAA`, and `LDRAB`.
44 API OFFSET(41) NUMBITS(1) [
45 EnableTrapPointerAuthInstToEl2 = 0,
46 DisableTrapPointerAuthInstToEl2 = 1
47 ],
48
49 /// Trap registers holding "key" values for Pointer Authentication. Traps accesses to the
50 /// following registers from EL1 to EL2, when EL2 is enabled in the current Security state,
51 /// reported using EC syndrome value 0x18:
52 ///
53 /// `APIAKeyLo_EL1`, `APIAKeyHi_EL1`, `APIBKeyLo_EL1`, `APIBKeyHi_EL1`, `APDAKeyLo_EL1`,
54 /// `APDAKeyHi_EL1`, `APDBKeyLo_EL1`, `APDBKeyHi_EL1`, `APGAKeyLo_EL1`, and `APGAKeyHi_EL1`.
55 APK OFFSET(40) NUMBITS(1) [
56 EnableTrapPointerAuthKeyRegsToEl2 = 0,
57 DisableTrapPointerAuthKeyRegsToEl2 = 1,
58 ],
59
60 /// Route synchronous External abort exceptions to EL2.
61 /// if 0: This control does not cause exceptions to be routed from EL0 and EL1 to EL2.
62 /// if 1: Route synchronous External abort exceptions from EL0 and EL1 to EL2, when EL2 is
63 /// enabled in the current Security state, if not routed to EL3.
64 TEA OFFSET(37) NUMBITS(1) [
65 DisableTrapSyncExtAbortsToEl2 = 0,
66 EnableTrapSyncExtAbortsToEl2 = 1,
67 ],
68
69 /// EL2 Host. Enables a configuration where a Host Operating System is running in EL2, and
70 /// the Host Operating System's applications are running in EL0.
71 E2H OFFSET(34) NUMBITS(1) [
72 DisableOsAtEl2 = 0,
73 EnableOsAtEl2 = 1
74 ],
75
76 /// Execution state control for lower Exception levels:
77 ///
78 /// 0 Lower levels are all AArch32.
79 /// 1 The Execution state for EL1 is AArch64. The Execution state for EL0 is determined by
80 /// the current value of PSTATE.nRW when executing at EL0.
81 ///
82 /// If all lower Exception levels cannot use AArch32 then this bit is RAO/WI.
83 ///
84 /// In an implementation that includes EL3, when SCR_EL3.NS==0, the PE behaves as if this
85 /// bit has the same value as the SCR_EL3.RW bit for all purposes other than a direct read
86 /// or write access of HCR_EL2.
87 ///
88 /// The RW bit is permitted to be cached in a TLB.
89 ///
90 /// When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this
91 /// field behaves as 1 for all purposes other than a direct read of the value of this bit.
92 RW OFFSET(31) NUMBITS(1) [
93 AllLowerELsAreAarch32 = 0,
94 EL1IsAarch64 = 1
95 ],
96
97 /// Trap General Exceptions, from EL0.
98 ///
99 /// If enabled:
100 /// - When EL2 is not enabled in the current Security state, this control has no effect on
101 /// execution at EL0.
102 ///
103 /// - When EL2 is enabled in the current Security state, in all cases:
104 ///
105 /// - All exceptions that would be routed to EL1 are routed to EL2.
106 /// - If EL1 is using AArch64, the SCTLR_EL1.M field is treated as being 0 for all
107 /// purposes other than returning the result of a direct read of SCTLR_EL1.
108 /// - If EL1 is using AArch32, the SCTLR.M field is treated as being 0 for all
109 /// purposes other than returning the result of a direct read of SCTLR.
110 /// - All virtual interrupts are disabled.
111 /// - Any IMPLEMENTATION DEFINED mechanisms for signaling virtual interrupts are
112 /// disabled.
113 /// - An exception return to EL1 is treated as an illegal exception return.
114 /// - The MDCR_EL2.{TDRA, TDOSA, TDA, TDE} fields are treated as being 1 for all
115 /// purposes other than returning the result of a direct read of MDCR_EL2.
116 ///
117 /// - In addition, when EL2 is enabled in the current Security state, if:
118 ///
119 /// - HCR_EL2.E2H is 0, the Effective values of the HCR_EL2.{FMO, IMO, AMO} fields
120 /// are 1.
121 /// - HCR_EL2.E2H is 1, the Effective values of the HCR_EL2.{FMO, IMO, AMO} fields
122 /// are 0.
123 ///
124 /// - For further information on the behavior of this bit when E2H is 1, see 'Behavior of
125 /// HCR_EL2.E2H'.
126 TGE OFFSET(27) NUMBITS(1) [
127 DisableTrapGeneralExceptionsToEl2 = 0,
128 EnableTrapGeneralExceptionsToEl2 = 1,
129 ],
130
131 /// Default Cacheability.
132 ///
133 /// 0 This control has no effect on the Non-secure EL1&0 translation regime.
134 ///
135 /// 1 In Non-secure state:
136 /// - When EL1 is using AArch64, the PE behaves as if the value of the SCTLR_EL1.M field
137 /// is 0 for all purposes other than returning the value of a direct read of SCTLR_EL1.
138 ///
139 /// - When EL1 is using AArch32, the PE behaves as if the value of the SCTLR.M field is 0
140 /// for all purposes other than returning the value of a direct read of SCTLR.
141 ///
142 /// - The PE behaves as if the value of the HCR_EL2.VM field is 1 for all purposes other
143 /// than returning the value of a direct read of HCR_EL2.
144 ///
145 /// - The memory type produced by stage 1 of the EL1&0 translation regime is Normal
146 /// Non-Shareable, Inner Write-Back Read-Allocate Write-Allocate, Outer Write-Back
147 /// Read-Allocate Write-Allocate.
148 ///
149 /// This field has no effect on the EL2, EL2&0, and EL3 translation regimes.
150 ///
151 /// This field is permitted to be cached in a TLB.
152 ///
153 /// In an implementation that includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
154 /// as if this field is 0 for all purposes other than a direct read or write access of
155 /// HCR_EL2.
156 ///
157 /// When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this
158 /// field behaves as 0 for all purposes other than a direct read of the value of this field.
159 DC OFFSET(12) NUMBITS(1) [],
160
161 /// Physical SError interrupt routing.
162 /// - If bit is 1 when executing at any Exception level, and EL2 is enabled in the current
163 /// Security state:
164 /// - Physical SError interrupts are taken to EL2, unless they are routed to EL3.
165 /// - When the value of HCR_EL2.TGE is 0, then virtual SError interrupts are enabled.
166 AMO OFFSET(5) NUMBITS(1) [],
167
168 /// Physical IRQ Routing.
169 ///
170 /// If this bit is 0:
171 /// - When executing at Exception levels below EL2, and EL2 is enabled in the current
172 /// Security state:
173 /// - When the value of HCR_EL2.TGE is 0, Physical IRQ interrupts are not taken to EL2.
174 /// - When the value of HCR_EL2.TGE is 1, Physical IRQ interrupts are taken to EL2
175 /// unless they are routed to EL3.
176 /// - Virtual IRQ interrupts are disabled.
177 ///
178 /// If this bit is 1:
179 /// - When executing at any Exception level, and EL2 is enabled in the current Security
180 /// state:
181 /// - Physical IRQ interrupts are taken to EL2, unless they are routed to EL3.
182 /// - When the value of HCR_EL2.TGE is 0, then Virtual IRQ interrupts are enabled.
183 ///
184 /// If EL2 is enabled in the current Security state, and the value of HCR_EL2.TGE is 1:
185 /// - Regardless of the value of the IMO bit, physical IRQ Interrupts target EL2 unless
186 /// they are routed to EL3.
187 /// - When FEAT_VHE is not implemented, or if HCR_EL2.E2H is 0, this field behaves as 1
188 /// for all purposes other than a direct read of the value of this bit.
189 /// - When FEAT_VHE is implemented and HCR_EL2.E2H is 1, this field behaves as 0 for all
190 /// purposes other than a direct read of the value of this bit.
191 ///
192 /// For more information, see 'Asynchronous exception routing'.
193 IMO OFFSET(4) NUMBITS(1) [
194 DisableVirtualIRQ = 0,
195 EnableVirtualIRQ = 1,
196 ],
197
198 /// Physical FIQ Routing.
199 /// If this bit is 0:
200 /// - When executing at Exception levels below EL2, and EL2 is enabled in the current
201 /// Security state:
202 /// - When the value of HCR_EL2.TGE is 0, Physical FIQ interrupts are not taken to EL2.
203 /// - When the value of HCR_EL2.TGE is 1, Physical FIQ interrupts are taken to EL2
204 /// unless they are routed to EL3.
205 /// - Virtual FIQ interrupts are disabled.
206 ///
207 /// If this bit is 1:
208 /// - When executing at any Exception level, and EL2 is enabled in the current Security
209 /// state:
210 /// - Physical FIQ interrupts are taken to EL2, unless they are routed to EL3.
211 /// - When HCR_EL2.TGE is 0, then Virtual FIQ interrupts are enabled.
212 ///
213 /// If EL2 is enabled in the current Security state and the value of HCR_EL2.TGE is 1:
214 /// - Regardless of the value of the FMO bit, physical FIQ Interrupts target EL2 unless
215 /// they are routed to EL3.
216 /// - When FEAT_VHE is not implemented, or if HCR_EL2.E2H is 0, this field behaves as 1
217 /// for all purposes other than a direct read of the value of this bit.
218 /// - When FEAT_VHE is implemented and HCR_EL2.E2H is 1, this field behaves as 0 for all
219 /// purposes other than a direct read of the value of this bit.
220 ///
221 /// For more information, see 'Asynchronous exception routing'.
222 FMO OFFSET(3) NUMBITS(1) [
223 DisableVirtualFIQ = 0,
224 EnableVirtualFIQ = 1,
225 ],
226
227 /// Set/Way Invalidation Override. Causes Non-secure EL1 execution of the data cache
228 /// invalidate by set/way instructions to perform a data cache clean and invalidate by
229 /// set/way:
230 ///
231 /// 0 This control has no effect on the operation of data cache invalidate by set/way
232 /// instructions.
233 ///
234 /// 1 Data cache invalidate by set/way instructions perform a data cache clean and
235 /// invalidate by set/way.
236 ///
237 /// When the value of this bit is 1:
238 ///
239 /// AArch32: DCISW performs the same invalidation as a DCCISW instruction.
240 ///
241 /// AArch64: DC ISW performs the same invalidation as a DC CISW instruction.
242 ///
243 /// This bit can be implemented as RES 1.
244 ///
245 /// In an implementation that includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
246 /// as if this field is 0 for all purposes other than a direct read or write access of
247 /// HCR_EL2.
248 ///
249 /// When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other
250 /// than a direct read of this field.
251 SWIO OFFSET(1) NUMBITS(1) [],
252
253 /// Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime,
254 /// when EL2 is enabled in the current Security state. The possible values are:
255 ///
256 /// 0 EL1&0 stage 2 address translation disabled.
257 /// 1 EL1&0 stage 2 address translation enabled.
258 ///
259 /// When the value of this bit is 1, data cache invalidate instructions executed at EL1 perform
260 /// a data cache clean and invalidate. For the invalidate by set/way instruction this behavior
261 /// applies regardless of the value of the HCR_EL2.SWIO bit.
262 ///
263 /// This bit is permitted to be cached in a TLB.
264 ///
265 /// When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this
266 /// field behaves as 0 for all purposes other than a direct read of the value of this field.
267 VM OFFSET(0) NUMBITS(1) [
268 Disable = 0,
269 Enable = 1
270 ]
271 ]
272}
273
274pub struct Reg;
275
276impl Readable for Reg {
277 type T = u64;
278 type R = HCR_EL2::Register;
279
280 sys_coproc_read_raw!(u64, "HCR_EL2", "x");
281}
282
283impl Writeable for Reg {
284 type T = u64;
285 type R = HCR_EL2::Register;
286
287 sys_coproc_write_raw!(u64, "HCR_EL2", "x");
288}
289
290pub const HCR_EL2: Reg = Reg {};