cortex_a/registers/sctlr_el2.rs
1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6// - Andre Richter <andre.o.richter@gmail.com>
7// - Bradley Landherr <landhb@users.noreply.github.com>
8
9//! System Control Register - EL2
10//!
11//! Provides top level control of the system, including its memory system, at EL2.
12
13use tock_registers::{
14 interfaces::{Readable, Writeable},
15 register_bitfields,
16};
17
18register_bitfields! {u64,
19 pub SCTLR_EL2 [
20
21 /// Exception endianness. The possible values are:
22 ///
23 /// 0 Little endian.
24 /// 1 Big endian.
25 EE OFFSET(25) NUMBITS(1) [
26 Little = 0,
27 Big = 1
28 ],
29
30 /// When FEAT_ExS is implemented control if taking an exception to EL2 is a context
31 /// synchonizing event
32 EIS OFFSET(22) NUMBITS(1) [
33 IsNotSynch = 0,
34 IsSynch = 1
35 ],
36
37 /// When FEAT_IESB is implemented control if an implict ESB is added at each exception
38 /// and before each ERET to/from EL2
39 IESB OFFSET(21) NUMBITS(1) [
40 Disable = 0,
41 Enable = 1
42 ],
43
44 /// Force treatment of all memory regions with write permissions as XN.
45 /// The possible values are:
46 ///
47 /// 0 Regions with write permissions are not forced XN. This is the reset value.
48 /// 1 Regions with write permissions are forced XN.
49 WXN OFFSET(19) NUMBITS(1) [
50 Disable = 0,
51 Enable = 1
52 ],
53
54 /// Instruction Cache Control, two possible values:
55 ///
56 /// 0 All instruction access to Normal memory from EL2 are Non-cacheable for all
57 /// levels of instruction and unified cache.
58 ///
59 /// If the value of SCTLR_EL2.M is 0, instruction accesses from stage 1 of the EL2 or EL2&0
60 /// translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer
61 /// Non-cacheable memory.
62 ///
63 /// 1 This control has no effect on the Cacheability of instruction access to Normal memory
64 /// from EL2 and, when EL2 is enabled in the current Security state and
65 /// HCR_EL2.{E2H, TGE} == {1, 1}, instruction access to Normal memory from EL0.
66 ///
67 /// If the value of SCTLR_EL2.M is 0, instruction accesses from stage 1 of the EL2&0
68 /// translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer
69 /// Write-Through memory.
70 ///
71 /// When EL2 is disabled, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit
72 /// has no effect on the PE.
73 ///
74 /// On a Warm reset, in a system where the PE resets into EL2, this field resets to 0.
75 I OFFSET(12) NUMBITS(1) [
76 NonCacheable = 0,
77 Cacheable = 1
78 ],
79
80 /// SP Alignment check enable.
81 ///
82 /// When set to 1, if a load or store instruction executed at EL2 uses the SP
83 /// as the base address and the SP is not aligned to a 16-byte boundary,
84 /// then a SP alignment fault exception is generated.
85 SA OFFSET(3) NUMBITS(1) [
86 Disable = 0,
87 Enable = 1
88 ],
89
90 /// Cacheability control, for data accesses.
91 ///
92 /// 0 The following are Non-cacheable for all levels of data and unified cache:
93 /// - Data accesses to Normal memory from EL2.
94 /// - When HCR_EL2.{E2H, TGE} != {1, 1}, Normal memory accesses to the EL2 translation tables.
95 /// - When EL2 is enabled in the current Security state and HCR_EL2.{E2H, TGE} == {1, 1}:
96 /// - Data accesses to Normal memory from EL0.
97 /// - Normal memory accesses to the EL2&0 translation tables.
98 ///
99 /// 1 This control has no effect on the Cacheability of:
100 /// - Data access to Normal memory from EL2.
101 /// - When HCR_EL2.{E2H, TGE} != {1, 1}, Normal memory accesses to the EL2 translation tables.
102 /// - When EL2 is enabled in the current Security state and HCR_EL2.{E2H, TGE} == {1, 1}:
103 /// - Data accesses to Normal memory from EL0.
104 /// - Normal memory accesses to the EL2&0 translation tables.
105 ///
106 /// When EL2 is disabled in the current Security state or HCR_EL2.{E2H, TGE} != {1, 1},
107 /// this bit has no effect on the EL1&0 translation regime.
108 ///
109 /// On a Warm reset, in a system where the PE resets into EL2, this field resets to 0.
110 C OFFSET(2) NUMBITS(1) [
111 NonCacheable = 0,
112 Cacheable = 1
113 ],
114
115 /// Alignment check enable. This is the enable bit for Alignment fault checking at EL2 and,
116 /// when EL2 is enabled in the current Security state and HCR_EL2.{E2H, TGE} == {1, 1}, EL0.
117 ///
118 /// Instructions that load or store one or more registers, other than load/store exclusive
119 /// and load-acquire/store-release, will or will not check that the address being accessed
120 /// is aligned to the size of the data element(s) being accessed depending on this flag.
121 ///
122 /// Load/store exclusive and load-acquire/store-release instructions have an alignment check
123 /// regardless of the value of the A bit.
124 A OFFSET(1) NUMBITS(1) [
125 Disable = 0,
126 Enable = 1
127 ],
128
129 /// MMU enable for EL2 or EL2&0 stage 1 address translation. Possible values of this bit are:
130 ///
131 /// 0 - When HCR_EL2.{E2H, TGE} != {1, 1}, EL2 stage 1 address translation disabled.
132 /// - When HCR_EL2.{E2H, TGE} == {1, 1}, EL2&0 stage 1 address translation disabled.
133 /// - See the SCTLR_EL2.I field for the behavior of instruction accesses to Normal memory.
134 ///
135 /// 1 - When HCR_EL2.{E2H, TGE} != {1, 1}, EL2 stage 1 address translation enabled.
136 /// - When HCR_EL2.{E2H, TGE} == {1, 1}, EL2&0 stage 1 address translation enabled.
137 ///
138 /// On a Warm reset, in a system where the PE resets into EL2, this field resets to 0.
139 M OFFSET(0) NUMBITS(1) [
140 Disable = 0,
141 Enable = 1
142 ]
143 ]
144}
145
146pub struct Reg;
147
148impl Readable for Reg {
149 type T = u64;
150 type R = SCTLR_EL2::Register;
151
152 sys_coproc_read_raw!(u64, "SCTLR_EL2", "x");
153}
154
155impl Writeable for Reg {
156 type T = u64;
157 type R = SCTLR_EL2::Register;
158
159 sys_coproc_write_raw!(u64, "SCTLR_EL2", "x");
160}
161
162pub const SCTLR_EL2: Reg = Reg {};