cortex_a/registers/
spsr_el2.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7
8//! Saved Program Status Register - EL2
9//!
10//! Holds the saved process state when an exception is taken to EL2.
11
12use tock_registers::{
13    interfaces::{Readable, Writeable},
14    register_bitfields,
15};
16
17register_bitfields! {u64,
18    pub SPSR_EL2 [
19        /// Negative condition flag.
20        ///
21        /// Set to the value of the N condition flag on taking an exception to EL2, and copied to
22        /// the N condition flag on executing an exception return operation in EL2.
23        ///
24        /// Set to 1 if the result of the last flag-setting instruction was negative.
25        N OFFSET(31) NUMBITS(1) [],
26
27        /// Zero condition flag.
28        ///
29        /// Set to the value of the Z condition flag on taking an exception to EL2, and copied to
30        /// the Z condition flag on executing an exception return operation in EL2.
31        ///
32        /// Set to 1 if the result of the last flag-setting instruction was zero, and to 0
33        /// otherwise. A result of zero often indicates an equal result from a comparison.
34        Z OFFSET(30) NUMBITS(1) [],
35
36        /// Carry condition flag.
37        ///
38        /// Set to the value of the C condition flag on taking an exception to EL2, and copied to
39        /// the C condition flag on executing an exception return operation in EL2.
40        ///
41        /// Set to 1 if the last flag-setting instruction resulted in a carry condition, for example
42        /// an unsigned overflow on an addition.
43        C OFFSET(29) NUMBITS(1) [],
44
45        /// Overflow condition flag.
46        ///
47        /// Set to the value of the V condition flag on taking an exception to EL2, and copied to
48        /// the V condition flag on executing an exception return operation in EL2.
49        ///
50        /// Set to 1 if the last flag-setting instruction resulted in an overflow condition, for
51        /// example a signed overflow on an addition.
52        V OFFSET(28) NUMBITS(1) [],
53
54        /// Software step. Shows the value of PSTATE.SS immediately before the exception was taken.
55        SS OFFSET(21) NUMBITS(1) [],
56
57        /// Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the
58        /// exception was taken.
59        IL OFFSET(20) NUMBITS(1) [],
60
61        /// Process state D mask. The possible values of this bit are:
62        ///
63        /// 0 Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception
64        ///   level are not masked.
65        ///
66        /// 1 Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception
67        ///   level are masked.
68        ///
69        /// When the target Exception level of the debug exception is higher than the current
70        /// Exception level, the exception is not masked by this bit.
71        D OFFSET(9) NUMBITS(1) [
72            Unmasked = 0,
73            Masked = 1
74        ],
75
76        /// SError interrupt mask bit. The possible values of this bit are:
77        ///
78        /// 0 Exception not masked.
79        /// 1 Exception masked.
80        A OFFSET(8) NUMBITS(1) [
81            Unmasked = 0,
82            Masked = 1
83        ],
84
85        /// IRQ mask bit. The possible values of this bit are:
86        ///
87        /// 0 Exception not masked.
88        /// 1 Exception masked.
89        I OFFSET(7) NUMBITS(1) [
90            Unmasked = 0,
91            Masked = 1
92        ],
93
94        /// FIQ mask bit. The possible values of this bit are:
95        ///
96        /// 0 Exception not masked.
97        /// 1 Exception masked.
98        F OFFSET(6) NUMBITS(1) [
99            Unmasked = 0,
100            Masked = 1
101        ],
102
103        /// AArch64 state (Exception level and selected SP) that an exception was taken from. The
104        /// possible values are:
105        ///
106        /// M[3:0] | State
107        /// --------------
108        /// 0b0000 | EL0t
109        /// 0b0100 | EL1t
110        /// 0b0101 | EL1h
111        /// 0b1000 | EL2t
112        /// 0b1001 | EL2h
113        ///
114        /// Other values are reserved, and returning to an Exception level that is using AArch64
115        /// with a reserved value in this field is treated as an illegal exception return.
116        ///
117        /// The bits in this field are interpreted as follows:
118        ///   - M[3:2] holds the Exception Level.
119        ///   - M[1] is unused and is RES 0 for all non-reserved values.
120        ///   - M[0] is used to select the SP:
121        ///     - 0 means the SP is always SP0.
122        ///     - 1 means the exception SP is determined by the EL.
123        M OFFSET(0) NUMBITS(4) [
124            EL0t = 0b0000,
125            EL1t = 0b0100,
126            EL1h = 0b0101,
127            EL2t = 0b1000,
128            EL2h = 0b1001
129        ]
130    ]
131}
132
133pub struct Reg;
134
135impl Readable for Reg {
136    type T = u64;
137    type R = SPSR_EL2::Register;
138
139    sys_coproc_read_raw!(u64, "SPSR_EL2", "x");
140}
141
142impl Writeable for Reg {
143    type T = u64;
144    type R = SPSR_EL2::Register;
145
146    sys_coproc_write_raw!(u64, "SPSR_EL2", "x");
147}
148
149pub const SPSR_EL2: Reg = Reg {};
cortex_a/registers/spsr_el2.rs

cortex_a/registers/
spsr_el2.rs
