cortex_a/registers/
id_aa64mmfr2_el1.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6//   - Valentin B. <valentin.be@protonmail.com>
7
8//! AArch64 Memory Model Feature Register 2 - EL1
9//!
10//! Provides information about the implemented memory model and memory
11//! management support in AArch64 state.
12
13use tock_registers::{interfaces::Readable, register_bitfields};
14
15register_bitfields! {u64,
16    pub ID_AA64MMFR2_EL1 [
17        /// Indicates support for the E0PD mechanism.
18        E0PD OFFSET(60) NUMBITS(4) [],
19
20        /// Enhanced Virtualization Traps.
21        ///
22        /// If EL2 is implemented, indicates support for the
23        /// HCR_EL2.{TTLBOS, TTLBIS, TOCU, TICAB, TID4} traps.
24        EVT OFFSET(56) NUMBITS(4) [
25            /// None of the aforementioned traps are supported.
26            Nothing = 0b0000,
27            /// All aforementioned traps but the HCR_EL2.{TTLBOS, TTLBBIS}
28            /// ones are supported.
29            NoTtl = 0b0001,
30            /// All the aforementioned HCR_EL2 traps are supported.
31            Everything = 0b0010
32        ],
33
34        /// Allows identification of the requirements of the hardware to have
35        /// break-before-make sequences when changing block size for a translation.
36        BBM OFFSET(52) NUMBITS(4) [
37            /// Level 0 support for changing block size is supported.
38            Level0 = 0b0000,
39            /// Level 1 support for changing block size is supported.
40            Level1 = 0b0001,
41            /// Level 2 support for changing block size is supported.
42            Level2 = 0b0010
43        ],
44
45        /// Indicates support for TTL field in address operations.
46        TTL OFFSET(48) NUMBITS(4) [],
47
48        /// Indicates support for HCR_EL2.FWB.
49        FWB OFFSET(40) NUMBITS(4) [],
50
51        /// Indicates the value of ESR_ELx.EC that reports an exception generated by
52        /// a read access to the feature ID space.
53        ///
54        /// - When reading 0, only read access exceptions other than HCR_EL2.TIDx,
55        /// SCTLR_EL1.UCT, or SCTLR_EL2.UCT traps are reported by ESR_ELx.EC == 0.
56        ///
57        /// - When reading 1, all read access exceptions are reported by ESR_ELx.EC == 0x18.
58        IDS OFFSET(36) NUMBITS(4) [],
59
60        /// Identifies support for unaligned single-copy atomicity and atomic functions.
61        AT OFFSET(32) NUMBITS(4) [],
62
63        /// Identifies support for small translation tables.
64        ST OFFSET(28) NUMBITS(4) [],
65
66        /// If EL2 is implemented, indicates support for the use of nested virtualization.
67        NV OFFSET(24) NUMBITS(4) [
68            /// Nested virtualization is not supported.
69            Unsupported = 0b0000,
70            /// The HCR_EL2.{AT, NV1, NV} bits are implemented.
71            Partial = 0b001,
72            /// The VNCR_EL2 register and the HCR_EL2.{NV2, AT, NV1, NV} bits are implemented.
73            Full = 0b0010
74        ],
75
76        /// Support for the use of revised `CCSIDR_EL1` register format.
77        CCIDX OFFSET(20) NUMBITS(4) [],
78
79        /// Indicates support for a larger virtual address.
80        ///
81        /// When this reads 1, 52-bit VAs when using the 64KB translation granule are
82        /// supported along with the standard 48-bit VAs.
83        VARange OFFSET(16) NUMBITS(4) [],
84
85        /// Indicates support for the IESB bit in the SCTLR_ELx registers.
86        IESB OFFSET(12) NUMBITS(4) [],
87
88        /// Indicates support for LSMAOE and nTLSMD bits in SCTLR_EL1 and SCTLR_EL2.
89        LSM OFFSET(8) NUMBITS(4) [],
90
91        /// Indicates support for User Access Overrides.
92        UAO OFFSET(4) NUMBITS(4) [],
93
94        /// Indicates support for Common not Private translations.
95        CnP OFFSET(0) NUMBITS(4) []
96    ]
97}
98
99pub struct Reg;
100
101impl Readable for Reg {
102    type T = u64;
103    type R = ID_AA64MMFR2_EL1::Register;
104
105    sys_coproc_read_raw!(u64, "ID_AA64MMFR2_EL1", "x");
106}
107
108pub const ID_AA64MMFR2_EL1: Reg = Reg;
cortex_a/registers/id_aa64mmfr2_el1.rs

cortex_a/registers/
id_aa64mmfr2_el1.rs
