cortex_a/registers/
esr_el1.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7//   - Berkus Decker <berkus+github@metta.systems>
8
9//! Exception Syndrome Register - EL1
10//!
11//! Holds syndrome information for an exception taken to EL1.
12
13use tock_registers::{interfaces::Readable, register_bitfields};
14
15register_bitfields! {u64,
16    pub ESR_EL1 [
17        /// Exception Class. Indicates the reason for the exception that this register holds
18        /// information about.
19        ///
20        /// For each EC value, the table references a subsection that gives information about:
21        ///   - The cause of the exception, for example the configuration required to enable the
22        ///     trap.
23        ///   - The encoding of the associated ISS.
24        ///
25        /// Incomplete listing - to be done.
26        EC  OFFSET(26) NUMBITS(6) [
27            Unknown               = 0b00_0000,
28            TrappedWFIorWFE       = 0b00_0001,
29            TrappedMCRorMRC       = 0b00_0011, // A32
30            TrappedMCRRorMRRC     = 0b00_0100, // A32
31            TrappedMCRorMRC2      = 0b00_0101, // A32
32            TrappedLDCorSTC       = 0b00_0110, // A32
33            TrappedFP             = 0b00_0111,
34            TrappedMRRC           = 0b00_1100, // A32
35            BranchTarget          = 0b00_1101,
36            IllegalExecutionState = 0b00_1110,
37            SVC32                 = 0b01_0001, // A32
38            SVC64                 = 0b01_0101,
39            HVC64                 = 0b01_0110,
40            SMC64                 = 0b01_0111,
41            TrappedMsrMrs         = 0b01_1000,
42            TrappedSve            = 0b01_1001,
43            PointerAuth           = 0b01_1100,
44            InstrAbortLowerEL     = 0b10_0000,
45            InstrAbortCurrentEL   = 0b10_0001,
46            PCAlignmentFault      = 0b10_0010,
47            DataAbortLowerEL      = 0b10_0100,
48            DataAbortCurrentEL    = 0b10_0101,
49            SPAlignmentFault      = 0b10_0110,
50            TrappedFP32           = 0b10_1000, // A32
51            TrappedFP64           = 0b10_1100,
52            SError                = 0b10_1111,
53            BreakpointLowerEL     = 0b11_0000,
54            BreakpointCurrentEL   = 0b11_0001,
55            SoftwareStepLowerEL   = 0b11_0010,
56            SoftwareStepCurrentEL = 0b11_0011,
57            WatchpointLowerEL     = 0b11_0100,
58            WatchpointCurrentEL   = 0b11_0101,
59            Bkpt32                = 0b11_1000, // A32 BKTP instruction
60            Brk64                 = 0b11_1100  // A64 BRK instruction
61        ],
62
63        /// Instruction Length for synchronous exceptions.
64        IL  OFFSET(25) NUMBITS(1) [],
65
66        /// Instruction Specific Syndrome. Architecturally, this field can be defined independently
67        /// for each defined Exception class. However, in practice, some ISS encodings are used for
68        /// more than one Exception class.
69        ISS OFFSET(0)  NUMBITS(25) []
70    ]
71}
72
73pub struct Reg;
74
75impl Readable for Reg {
76    type T = u64;
77    type R = ESR_EL1::Register;
78
79    sys_coproc_read_raw!(u64, "ESR_EL1", "x");
80}
81
82pub const ESR_EL1: Reg = Reg {};
cortex_a/registers/esr_el1.rs

cortex_a/registers/
esr_el1.rs
