cortex_a/registers/
daif.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7
8//! Interrupt Mask Bits
9//!
10//! Allows access to the interrupt mask bits.
11
12use tock_registers::{
13    interfaces::{Readable, Writeable},
14    register_bitfields,
15};
16
17register_bitfields! {u64,
18    pub DAIF [
19        /// Process state D mask. The possible values of this bit are:
20        ///
21        /// 0 Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception
22        ///   level are not masked.
23        ///
24        /// 1 Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception
25        ///   level are masked.
26        ///
27        /// When the target Exception level of the debug exception is higher than the current
28        /// Exception level, the exception is not masked by this bit.
29        ///
30        /// When this register has an architecturally-defined reset value, this field resets to 1.
31        D OFFSET(9) NUMBITS(1) [
32            Unmasked = 0,
33            Masked = 1
34        ],
35
36        /// SError interrupt mask bit. The possible values of this bit are:
37        ///
38        /// 0 Exception not masked.
39        /// 1 Exception masked.
40        ///
41        /// When this register has an architecturally-defined reset value, this field resets to 1.
42        A OFFSET(8) NUMBITS(1) [
43            Unmasked = 0,
44            Masked = 1
45        ],
46
47        /// IRQ mask bit. The possible values of this bit are:
48        ///
49        /// 0 Exception not masked.
50        /// 1 Exception masked.
51        ///
52        /// When this register has an architecturally-defined reset value, this field resets to 1.
53        I OFFSET(7) NUMBITS(1) [
54            Unmasked = 0,
55            Masked = 1
56        ],
57
58        /// FIQ mask bit. The possible values of this bit are:
59        ///
60        /// 0 Exception not masked.
61        /// 1 Exception masked.
62        ///
63        /// When this register has an architecturally-defined reset value, this field resets to 1.
64        F OFFSET(6) NUMBITS(1) [
65            Unmasked = 0,
66            Masked = 1
67        ]
68    ]
69}
70
71pub struct Reg;
72
73impl Readable for Reg {
74    type T = u64;
75    type R = DAIF::Register;
76
77    sys_coproc_read_raw!(u64, "DAIF", "x");
78}
79
80impl Writeable for Reg {
81    type T = u64;
82    type R = DAIF::Register;
83
84    sys_coproc_write_raw!(u64, "DAIF", "x");
85}
86
87pub const DAIF: Reg = Reg {};
cortex_a/registers/daif.rs

cortex_a/registers/
daif.rs
