cortex_a/registers/tcr_el1.rs
1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6// - Andre Richter <andre.o.richter@gmail.com>
7
8//! Translation Control Register - EL1
9//!
10//! The control register for stage 1 of the EL1&0 translation regime.
11
12use tock_registers::{
13 interfaces::{Readable, Writeable},
14 register_bitfields,
15};
16
17register_bitfields! {u64,
18 pub TCR_EL1 [
19 /// When ARMv8.3-PAuth is implemented:
20 /// Controls the use of the top byte of instruction addresses for address matching.
21 /// 0 TCR_EL1.TBI1 applies to Instruction and Data accesses.
22 /// 1 TCR_EL1.TBI1 applies to Data accesses only.
23 /// This affects addresses where the address would be translated by tables pointed
24 /// to by TTBR1_EL1. This field resets to an architecturally UNKNOWN value.
25 /// Otherwise:
26 /// Reserved, RES0.
27 TBID1 OFFSET(52) NUMBITS(1) [],
28
29 /// When ARMv8.3-PAuth is implemented:
30 /// Controls the use of the top byte of instruction addresses for address matching.
31 /// 0 TCR_EL1.TBI0 applies to Instruction and Data accesses.
32 /// 1 TCR_EL1.TBI0 applies to Data accesses only.
33 /// This affects addresses where the address would be translated by tables pointed
34 /// to by TTBR0_EL1. This field resets to an architecturally UNKNOWN value.
35 /// Otherwise:
36 /// Reserved, RES0.
37 TBID0 OFFSET(51) NUMBITS(1) [],
38
39 /// When FEAT_HAFDBS is implemented hardware can update the dirty flags in the stage1
40 /// descriptors
41 HD OFFSET(40) NUMBITS(1) [
42 Disable = 0,
43 Enable = 1,
44 ],
45
46 /// When FEAT_HAFDBS is implemented hardware can update the access flags in the stage1
47 /// descriptors
48 HA OFFSET(39) NUMBITS(1) [
49 Disable = 0,
50 Enable = 1,
51 ],
52
53 /// Top Byte ignored - indicates whether the top byte of an address is used for address
54 /// match for the TTBR1_EL1 region, or ignored and used for tagged addresses. Defined values
55 /// are:
56 ///
57 /// 0 Top Byte used in the address calculation.
58 ///
59 /// 1 Top Byte ignored in the address calculation.
60 ///
61 /// This affects addresses generated in EL0 and EL1 using AArch64 where the address would be
62 /// translated by tables pointed to by TTBR1_EL1. It has an effect whether the EL1&0
63 /// translation regime is enabled or not.
64 ///
65 /// If ARMv8.3-PAuth is implemented and TCR_EL1.TBID1 is 1, then this field only applies to
66 /// Data accesses.
67 /// Otherwise, if the value of TBI1 is 1 and bit [55] of the target address to be stored to
68 /// the PC is 0, then bits[63:56] of that target address are also set to 0 before the
69 /// address is stored in the PC, in the following cases:
70 ///
71 /// • A branch or procedure return within EL0 or EL1.
72 /// • An exception taken to EL1.
73 /// • An exception return to EL0 or EL1.
74 TBI1 OFFSET(38) NUMBITS(1) [
75 Used = 0,
76 Ignored = 1
77 ],
78
79 /// Top Byte ignored - indicates whether the top byte of an address is used for address
80 /// match for the TTBR0_EL1 region, or ignored and used for tagged addresses. Defined values
81 /// are:
82 ///
83 /// 0 Top Byte used in the address calculation.
84 ///
85 /// 1 Top Byte ignored in the address calculation.
86 ///
87 /// This affects addresses generated in EL0 and EL1 using AArch64 where the address would be
88 /// translated by tables pointed to by TTBR0_EL1. It has an effect whether the EL1&0
89 /// translation regime is enabled or not.
90 ///
91 /// If ARMv8.3-PAuth is implemented and TCR_EL1.TBID0 is 1, then this field only applies to
92 /// Data accesses.
93 /// Otherwise, if the value of TBI0 is 1 and bit [55] of the target address to be stored to
94 /// the PC is 0, then bits[63:56] of that target address are also set to 0 before the
95 /// address is stored in the PC, in the following cases:
96 ///
97 /// • A branch or procedure return within EL0 or EL1.
98 /// • An exception taken to EL1.
99 /// • An exception return to EL0 or EL1.
100 TBI0 OFFSET(37) NUMBITS(1) [
101 Used = 0,
102 Ignored = 1
103 ],
104
105 /// ASID Size. Defined values are:
106 ///
107 /// 0 8 bit - the upper 8 bits of TTBR0_EL1 and TTBR1_EL1 are ignored by hardware for every
108 /// purpose except reading back the register, and are treated as if they are all
109 /// zeros for when used for allocation and matching entries in the TLB.
110 ///
111 /// 1 16 bit - the upper 16 bits of TTBR0_EL1 and TTBR1_EL1 are used for allocation and
112 /// matching in the TLB.
113 ///
114 /// If the implementation has only 8 bits of ASID, this field is RES0.
115 AS OFFSET(36) NUMBITS(1) [
116 ASID8Bits = 0,
117 ASID16Bits = 1
118 ],
119
120 /// Intermediate Physical Address Size.
121 ///
122 /// 000 32 bits, 4GiB.
123 /// 001 36 bits, 64GiB.
124 /// 010 40 bits, 1TiB.
125 /// 011 42 bits, 4TiB.
126 /// 100 44 bits, 16TiB.
127 /// 101 48 bits, 256TiB.
128 /// 110 52 bits, 4PiB
129 ///
130 /// Other values are reserved.
131 ///
132 /// The reserved values behave in the same way as the 101 or 110 encoding, but software must
133 /// not rely on this property as the behavior of the reserved values might change in a
134 /// future revision of the architecture.
135 ///
136 /// The value 110 is permitted only if ARMv8.2-LPA is implemented and the translation
137 /// granule size is 64KiB.
138 ///
139 /// In an implementation that supports 52-bit PAs, if the value of this field is not 110 ,
140 /// then bits[51:48] of every translation table base address for the stage of translation
141 /// controlled by TCR_EL1 are 0000.
142 IPS OFFSET(32) NUMBITS(3) [
143 Bits_32 = 0b000,
144 Bits_36 = 0b001,
145 Bits_40 = 0b010,
146 Bits_42 = 0b011,
147 Bits_44 = 0b100,
148 Bits_48 = 0b101,
149 Bits_52 = 0b110
150 ],
151
152 /// Granule size for the TTBR1_EL1.
153 ///
154 /// 10 4KiB
155 /// 01 16KiB
156 /// 11 64KiB
157 ///
158 /// Other values are reserved.
159 ///
160 /// If the value is programmed to either a reserved value, or a size that has not been
161 /// implemented, then the hardware will treat the field as if it has been programmed to an
162 /// IMPLEMENTATION DEFINED choice of the sizes that has been implemented for all purposes
163 /// other than the value read back from this register.
164 ///
165 /// It is IMPLEMENTATION DEFINED whether the value read back is the value programmed or the
166 /// value that corresponds to the size chosen.
167 TG1 OFFSET(30) NUMBITS(2) [
168 KiB_4 = 0b10,
169 KiB_16 = 0b01,
170 KiB_64 = 0b11
171 ],
172
173 /// Shareability attribute for memory associated with translation table walks using
174 /// TTBR1_EL1.
175 ///
176 /// 00 Non-shareable
177 /// 10 Outer Shareable
178 /// 11 Inner Shareable
179 ///
180 /// Other values are reserved.
181 SH1 OFFSET(28) NUMBITS(2) [
182 None = 0b00,
183 Outer = 0b10,
184 Inner = 0b11
185 ],
186
187 /// Outer cacheability attribute for memory associated with translation table walks using
188 /// TTBR1_EL1.
189 ///
190 /// 00 Normal memory, Outer Non-cacheable
191 ///
192 /// 01 Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable
193 ///
194 /// 10 Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable
195 ///
196 /// 11 Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable
197 ORGN1 OFFSET(26) NUMBITS(2) [
198 NonCacheable = 0b00,
199 WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01,
200 WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10,
201 WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11
202 ],
203
204 /// Inner cacheability attribute for memory associated with translation
205 /// table walks using TTBR1_EL1.
206 ///
207 /// 00 Normal memory, Inner Non-cacheable
208 ///
209 /// 01 Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable
210 ///
211 /// 10 Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable
212 ///
213 /// 11 Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable
214 IRGN1 OFFSET(24) NUMBITS(2) [
215 NonCacheable = 0b00,
216 WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01,
217 WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10,
218 WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11
219 ],
220
221 /// Translation table walk disable for translations using TTBR1_EL1. This bit controls
222 /// whether a translation table walk is performed on a TLB miss, for an address that is
223 /// translated using TTBR1_EL1. The encoding of this bit is:
224 ///
225 /// 0 Perform translation table walks using TTBR1_EL1.
226 ///
227 /// 1 A TLB miss on an address that is translated using TTBR1_EL1 generates a Translation
228 /// fault. No translation table walk is performed.
229 EPD1 OFFSET(23) NUMBITS(1) [
230 EnableTTBR1Walks = 0,
231 DisableTTBR1Walks = 1
232 ],
233
234 /// Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID. The encoding of this bit is:
235 ///
236 /// 0 TTBR0_EL1.ASID defines the ASID.
237 /// 1 TTBR1_EL1.ASID defines the ASID.
238 A1 OFFSET(22) NUMBITS(1) [
239 TTBR0 = 0,
240 TTBR1 = 1
241 ],
242
243 /// The size offset of the memory region addressed by TTBR1_EL1. The region size is
244 /// 2^(64-T1SZ) bytes.
245 ///
246 /// The maximum and minimum possible values for T1SZ depend on the level of translation
247 /// table and the memory translation granule size, as described in the AArch64 Virtual
248 /// Memory System Architecture chapter.
249 ///
250 /// This field resets to an architecturally UNKNOWN value.
251 T1SZ OFFSET(16) NUMBITS(6) [],
252
253 /// Granule size for the TTBR0_EL1.
254 ///
255 /// 00 4KiB
256 /// 01 64KiB
257 /// 10 16KiB
258 ///
259 /// Other values are reserved.
260 ///
261 /// If the value is programmed to either a reserved value, or a size that has not been
262 /// implemented, then the hardware will treat the field as if it has been programmed to an
263 /// IMPLEMENTATION DEFINED choice of the sizes that has been implemented for all purposes
264 /// other than the value read back from this register.
265 ///
266 /// It is IMPLEMENTATION DEFINED whether the value read back is the value programmed or the
267 /// value that corresponds to the size chosen.
268 TG0 OFFSET(14) NUMBITS(2) [
269 KiB_4 = 0b00,
270 KiB_16 = 0b10,
271 KiB_64 = 0b01
272 ],
273
274 /// Shareability attribute for memory associated with translation table walks using
275 /// TTBR0_EL1.
276 ///
277 /// 00 Non-shareable
278 /// 10 Outer Shareable
279 /// 11 Inner Shareable
280 ///
281 /// Other values are reserved.
282 SH0 OFFSET(12) NUMBITS(2) [
283 None = 0b00,
284 Outer = 0b10,
285 Inner = 0b11
286 ],
287
288 /// Outer cacheability attribute for memory associated with translation table walks using
289 /// TTBR0_EL1.
290 ///
291 /// 00 Normal memory, Outer Non-cacheable
292 ///
293 /// 01 Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable
294 ///
295 /// 10 Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable
296 ///
297 /// 11 Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable
298 ORGN0 OFFSET(10) NUMBITS(2) [
299 NonCacheable = 0b00,
300 WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01,
301 WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10,
302 WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11
303 ],
304
305 /// Inner cacheability attribute for memory associated with translation table walks using
306 /// TTBR0_EL1.
307 ///
308 /// 00 Normal memory, Inner Non-cacheable
309 ///
310 /// 01 Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable
311 ///
312 /// 10 Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable
313 ///
314 /// 11 Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable
315 IRGN0 OFFSET(8) NUMBITS(2) [
316 NonCacheable = 0b00,
317 WriteBack_ReadAlloc_WriteAlloc_Cacheable = 0b01,
318 WriteThrough_ReadAlloc_NoWriteAlloc_Cacheable = 0b10,
319 WriteBack_ReadAlloc_NoWriteAlloc_Cacheable = 0b11
320 ],
321
322 /// Translation table walk disable for translations using TTBR0_EL1. This bit controls
323 /// whether a translation table walk is performed on a TLB miss, for an address that is
324 /// translated using TTBR0_EL1. The encoding of this bit is:
325 ///
326 /// 0 Perform translation table walks using TTBR0_EL1.
327 ///
328 /// 1 A TLB miss on an address that is translated using TTBR0_EL1 generates a Translation
329 /// fault. No translation table walk is performed.
330 EPD0 OFFSET(7) NUMBITS(1) [
331 EnableTTBR0Walks = 0,
332 DisableTTBR0Walks = 1
333 ],
334
335 /// The size offset of the memory region addressed by TTBR0_EL1. The region size is
336 /// 2^(64-T0SZ) bytes.
337 ///
338 /// The maximum and minimum possible values for T0SZ depend on the level of translation
339 /// table and the memory translation granule size, as described in the AArch64 Virtual
340 /// Memory System Architecture chapter.
341 T0SZ OFFSET(0) NUMBITS(6) []
342 ]
343}
344
345pub struct Reg;
346
347impl Readable for Reg {
348 type T = u64;
349 type R = TCR_EL1::Register;
350
351 sys_coproc_read_raw!(u64, "TCR_EL1", "x");
352}
353
354impl Writeable for Reg {
355 type T = u64;
356 type R = TCR_EL1::Register;
357
358 sys_coproc_write_raw!(u64, "TCR_EL1", "x");
359}
360
361pub const TCR_EL1: Reg = Reg {};