cortex_a/registers/
csselr_el1.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6//   - Valentin B. <valentin.be@protonmail.com>
7
8//! Cache Size Selection Register - EL1
9//!
10//! Selects the current Cache Size ID Register, CCSIDR_EL1, by specifying the
11//! required cache level and the cache type (either instruction or data cache).
12
13use tock_registers::{
14    interfaces::{Readable, Writeable},
15    register_bitfields,
16};
17
18register_bitfields! {u64,
19    pub CSSELR_EL1 [
20        /// ** When `FEAT_MTE2` is implemented:**
21        ///
22        /// Allocation Tag not Data bit.
23        ///
24        /// When [`CSSELR_EL1::InD`] is set, this bit is considered reserved.
25        ///
26        /// When [`CSSELR_EL1::Level`] is programmed to a cache level that is
27        /// not implemented, this field's value will be undefined for reads.
28        ///
29        /// NOTE: On a Warm reset, this field resets to an architecturally
30        /// undefined value.
31        ///
32        /// **Otherwise:**
33        ///
34        /// Reserved.
35        TnD OFFSET(4) NUMBITS(1) [
36            /// Data, Instruction or Unified cache.
37            Data = 0b0,
38            /// Separate Allocation Tag cache.
39            AllocationTag = 0b1
40        ],
41
42        /// Cache level of required cache.
43        ///
44        /// Any value other than the pre-defined ones are considered reserved
45        /// and shall not be written to this field.
46        ///
47        /// When [`CSSELR_EL1::Level`] is programmed to a cache level that is
48        /// not implemented, this field's value will be undefined for reads.
49        ///
50        /// NOTE: On a Warm reset, this field resets to an architecturally
51        /// undefined value.
52        Level OFFSET(1) NUMBITS(3) [
53            /// Level 1 Cache.
54            L1 = 0b000,
55            /// Level 2 Cache.
56            L2 = 0b001,
57            /// Level 3 Cache.
58            L3 = 0b010,
59            /// Level 4 Cache.
60            L4 = 0b011,
61            /// Level 5 Cache.
62            L5 = 0b100,
63            /// Level 6 Cache.
64            L6 = 0b101,
65            /// Level 7 Cache.
66            L7 = 0b110
67        ],
68
69        /// Instruction not Data bit.
70        ///
71        /// When [`CSSELR_EL1::Level`] is programmed to a cache level that is
72        /// not implemented, this field's value will be undefined for reads.
73        ///
74        /// NOTE: On a Warm reset, this field resets to an architecturally
75        /// undefined value.
76        InD OFFSET(0) NUMBITS(1) [
77            /// Data or Unified cache.
78            Data = 0b0,
79            /// Instruction cache.
80            Instruction = 0b1
81        ]
82    ]
83}
84
85pub struct Reg;
86
87impl Readable for Reg {
88    type T = u64;
89    type R = CSSELR_EL1::Register;
90
91    sys_coproc_read_raw!(u64, "CSSELR_EL1", "x");
92}
93
94impl Writeable for Reg {
95    type T = u64;
96    type R = CSSELR_EL1::Register;
97
98    sys_coproc_write_raw!(u64, "CSSELR_EL1", "x");
99}
100
101pub const CSSELR_EL1: Reg = Reg;
cortex_a/registers/csselr_el1.rs

cortex_a/registers/
csselr_el1.rs
