cortex_a/registers/
cpacr_el1.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2022 by the author(s)
4//
5// Author(s):
6//   - Valentin B. <valentin.be@protonmail.com>
7
8//! Architectural Feature Access Control Register - EL1
9//!
10//! Controls access to trace, SVE, and Advanced SIMD and floating-point functionality.
11
12use tock_registers::{
13    interfaces::{Readable, Writeable},
14    register_bitfields,
15};
16
17register_bitfields! {u64,
18    pub CPACR_EL1 [
19        /// Traps EL0 and EL1 System register accesses to all implemented trace
20        /// registers from both Execution states to EL1, or to EL2 when it is
21        /// implemented and enabled in the current Security state and HCR_EL2.TGE
22        /// is 1, as follows:
23        ///
24        /// - In AArch64 state, accesses to trace registers are trapped, reported
25        /// using ESR_ELx.EC value 0x18.
26        ///
27        /// - In AArch32 state, MRC and MCR accesses to trace registers are trapped,
28        /// reported using ESR_ELx.EC value 0x05.
29        ///
30        /// - In AArch32 state, MCR and MCRR accesses to trace registers are trapped,
31        /// reported using ESR_ELx.EC value 0x0C.
32        ///
33        /// System register accesses to the trace registers can have side-effects.
34        /// When a System register access is trapped, any side-effects that are
35        /// normally associated with the access do not occur before the exception is
36        /// taken.
37        ///
38        /// If System register access to the trace functionality is not implemented,
39        /// this bit is considered reserved.
40        ///
41        /// On a Warm reset, this field resets to an undefined value.
42        TTA OFFSET(28) NUMBITS(1) [
43            /// This control does not cause any instructions to be trapped.
44            NoTrap = 0b0,
45            /// This control causes EL0 and EL1 System register accesses to all
46            /// implemented trace registers to be trapped.
47            TrapTrace = 0b1
48        ],
49
50        /// Traps execution at EL0 and EL1 of instructions that access the Advanced SIMD
51        /// and floating-point registers from both Execution states to EL1, reported using
52        /// ESR_ELx.EC value 0x07, or to EL2 reported using ESR_ELx.EC value 0x00 when EL2
53        /// is implemented and enabled in the current Security state and HCR_EL2.TGE is 1,
54        /// as follows:
55        ///
56        /// - In AArch64 state, accesses to FPCR, FPSR, any of the SIMD and floating-point
57        /// registers V0-V31, including their views as D0-31 registers or S0-31 registers.
58        ///
59        /// - In AArch32 state, FPSCR, and any of the SIMD and floating-point registers
60        /// Q0-15, including their views as D0-31 registers or S0-31 registers.
61        ///
62        /// Traps execution at EL1 and EL0 of SVE instructions to EL1, or to EL2 when El2
63        /// is implemented and enabled for the current Security state and HCR_EL2.TGE is 1.
64        /// The exception is reported using ESR_ELx.EC value 0x07.
65        ///
66        /// A trap taken as a result of [`CPACR_EL1::ZEN`] has precendence over a trap taken
67        /// as a result of [`CPACR_EL1::FPEN`].
68        ///
69        /// On a Warm reset, this fields resets to an undefined value.
70        FPEN OFFSET(20) NUMBITS(2) [
71            /// This control causes execution of these instructions at EL0 and EL1 to be trapped.
72            TrapEl0El1 = 0b00,
73            /// This control causes execution of these instructions at EL0 to be trapped, but
74            /// does not cause any instructions at EL1 to be trapped.
75            TrapEl0 = 0b01,
76            /// This control causes execution of these instructions at EL1 and EL0 to be trapped.
77            TrapEl1El0 = 0b10,
78            /// This control does not cause execution of any instructions to be trapped.
79            TrapNothing = 0b11
80        ],
81
82        /// **When FEAT_SVE is implemented:**
83        ///
84        /// Traps execution at EL1 and EL0 of SVE instructions and instructions that directly
85        /// access the ZCR_EL1 Systme register to EL1, or to EL2 when El2 is implemented in the
86        /// current Security state and HCR_EL2.TGE is 1.
87        ///
88        /// The exception is reported using ESR_ELx.EC value 0x19.
89        ///
90        /// A trap taken as a result of CPACR_EL1.ZEN has precedence over a trap taken as a result
91        /// of CPACR_EL1.FPEN.
92        ///
93        /// On a Warm reset, this field resets to an undefined value.
94        ///
95        /// **Otherwise:**
96        ///
97        /// Reserved.
98        ZEN OFFSET(16) NUMBITS(2) [
99            /// This control causes execution of these instructions at EL0 and EL1 to be trapped.
100            TrapEl0El1 = 0b00,
101            /// This control causes execution of these instructions at EL0 to be trapped, but
102            /// does not cause execution of any instructions at EL1 to be trapped.
103            TrapEl0 = 0b01,
104            /// This control causes execution of these instructions at EL1 and EL0 to be trapped.
105            TrapEl1El0 = 0b10,
106            /// This control does not cause execution of any instructions to be trapped.
107            TrapNothing = 0b11
108        ]
109    ]
110}
111
112pub struct Reg;
113
114impl Readable for Reg {
115    type T = u64;
116    type R = ();
117
118    sys_coproc_read_raw!(u64, "CPACR_EL1", "x");
119}
120
121impl Writeable for Reg {
122    type T = u64;
123    type R = ();
124
125    sys_coproc_write_raw!(u64, "CPACR_EL1", "x");
126}
127
128pub const CPACR_EL1: Reg = Reg;
cortex_a/registers/cpacr_el1.rs

cortex_a/registers/
cpacr_el1.rs
