Module cortex_a::registers::CPACR_EL1

source ·

Modules

FPEN
Traps execution at EL0 and EL1 of instructions that access the Advanced SIMD and floating-point registers from both Execution states to EL1, reported using ESR_ELx.EC value 0x07, or to EL2 reported using ESR_ELx.EC value 0x00 when EL2 is implemented and enabled in the current Security state and HCR_EL2.TGE is 1, as follows:
TTA
Traps EL0 and EL1 System register accesses to all implemented trace registers from both Execution states to EL1, or to EL2 when it is implemented and enabled in the current Security state and HCR_EL2.TGE is 1, as follows:
ZEN
When FEAT_SVE is implemented:

Structs

Register

Constants

FPEN
TTA
ZEN